Open Ephys 2.0 is a collection of ONI-compatible hardware, firmware, and API for serialized, very-high channel count, closed-loop electrophysiology. It is an evolution of the first-generation hardware and software introduced in Open Ephys project and involves many of the same developers. The firmware and API are general purpose -- they can be used to acquire from and control custom headstages with arbitrary arrangements of sensors and actuators (e.g. cameras, bioamplifier chips, LED drivers, etc.) and are not limited to the hardware in this repository.
Citing this work:
- Citing the paper
- TODO
- Citing the repository itself
-
Follows the ONI-specification for serialization protocols, host communication protocols, device drivers, and host API
-
Firmware and API permit acquisition and control of arbitrary arrangements of sensors and actuators:
- Headstages
- Miniscopes
- Photometry systems
- Etc.
-
Submillisecond round-trip communication from brain, through host PC's main memory, and back again.
-
Flagship headstages:
- 64-, 128-, 256-channels of electrophysiology
- Optogenetic stimulation
- Electrical stimulation
- 3D-pose measurement
- Data, user control, and power via a tiny coaxial cable
- Wireless communication
-
Low-level API implementation
-
High-level API language bindings and existing integration with Open Ephys GUI and Bonsai.
-
Quality documentation and easy routes to purchasing assembled devices.
Each top level directory of this repository corresponds to a distinct system
module. These can firmware (e.g. TODO), hardware components (e.g.
headstage-64), or programming interfaces (e.g. api). Each subdirectory
may have distinct contributors and/or licenses. Please refer to the README
file within each directory for further information on usage, licensing, etc.
The Open Neuro Interface formally specifies data serialization, host/PC communication, firmware blocks, device drivers and programming interfaces for this project. All firmware, software, and hardware artifacts in this repository are implementations of this specification. Therefore, third party implementations that maintain compatibility with ONI will interoperate with the software and hardware within this project.
High-performance, host-side programming interfaces for integration with existing software and the creation of high level language bindings.
- TODO: Myget distribution
- TODO: Integration into open-ephys master
Binary files for headstage and host FPGAs are available here. Firmware source code is currently available under controlled release. Contact the maintainer for more information.
64 Channel electrode interface board. Designed for small rodent tetrode electrophysiology. Works with headstage-64.
128 Channel electrode interface board. Designed for large rodent tetrode electrophysiology. Works with headstage-256.
256 Channel electrode interface board. Designed for large rodent tetrode electrophysiology. Works with headstage-256.
Serialized, multifunction headstage for small rodents. Supports 64 channels. Designed to interface with eib-64.
Serialized, multifunction headstage for large rodents. Supports both 128 or 256 channels. Designed to interface with eib-128 or eib-256
Base board for facilitating PCIe communication, via FMC compatiable and PCIe-capable FPGA based board (e.g. Numato Lab Nereid. This board plugs into the FMC connector on the base board. It provides communication with one headstage and lots of other analog and digital IO.
Passive breakout board for acquiring and generating analog signals through BNC, SMA, ribbon, or straight wire connections. Plugs into fmc-host using a 26-pin shrunk delta ribbon cable.
Adapter to interface eib-64 with the popular nanoZ electrode impedance tester and plating device.
Multiplexed adapter to interface eib-128 and eib-256 with the popular nanoZ electrode impedance tester and plating device.
Test board for headstage-64. Allows injecting simulated biopotentials into headstage modules via a selectable passive attenuator. Provides LEDs and simulated electrical loads for optical and electrical stimulation.
Test board for headstage, and headstage-256 modules. Allows injecting simulated biopotentials into headstage modules via a selectable passive attenuator. Provides LEDs and simulated electrical loads for optical and electrical stimulation.
JTAG breakout for the Intel USB Blaster 2 used to program the headstages' MAX10 FPGA.
General purpose analog IO expansion board which communicates with the host computer via the sits next to pcie-host board.