simulate core memory

[nczempin]

http://www.psych.usyd.edu.au/pdp-11/core.html: "Core memory is also fairly slow, with the early systems having a cycle time of up to 6µs. By the early 1970's, the cycle was down to 1.2µs, and within a few years it halved to 600ns. A technique called interleaving was used to speed up the access time for sequential memory locations. If you have two memory systems that are the same size, then the address decoding can be arranged so that every other memory location goes to a different memory system. This effectively doubles the speed of the memory system when sequential locations are accessed. Some large mainframe computers may have as many as 32 memory banks interleaved to gain speed."

this could go on a simulated or real external board.