Pinned Repositories
ariane
Ariane is a 6-stage RISC-V CPU
asciidoctor-lists
An asciidoctor extension that adds a list of figures, a list of tables, or a list of anything you want!
asciidoctor-multipage
A configurable multipage HTML converter for Asciidoctor
asciidoctor-skins
Control how your asciidoctor powered documentation looks
asciidoctor-theme
Asciidoctor theme
beri
The BERI and CHERI processor and hardware platform
BluespecIntroGuide
An introductory guide to Bluespec (BSV)
bsc-contrib
A place to share libraries and utilities that don't belong in the core bsc repo
chisel
riscv-sodor
educational microarchitectures for risc-v isa
neelgala's Repositories
neelgala/ariane
Ariane is a 6-stage RISC-V CPU
neelgala/asciidoctor-lists
An asciidoctor extension that adds a list of figures, a list of tables, or a list of anything you want!
neelgala/asciidoctor-multipage
A configurable multipage HTML converter for Asciidoctor
neelgala/asciidoctor-skins
Control how your asciidoctor powered documentation looks
neelgala/asciidoctor-theme
Asciidoctor theme
neelgala/BluespecIntroGuide
An introductory guide to Bluespec (BSV)
neelgala/bsc-contrib
A place to share libraries and utilities that don't belong in the core bsc repo
neelgala/docs-dev-guide
Documentation developer guide
neelgala/Experimental_RISCV_Feature_Model
An experimental DSL to describe the full feature list of a RISC-V implementation, along with constraints on features and between features
neelgala/imperas-riscv-tests
neelgala/neorv32
:desktop_computer: An area-optimized, customizable MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
neelgala/openc906
OpenXuantie - OpenC906 Core
neelgala/openc910
OpenXuantie - OpenC910 Core
neelgala/opene902
OpenXuantie - OpenE902 Core
neelgala/opene906
OpenXuantie - OpenE906 Core
neelgala/riscv-arch-test
neelgala/riscv-bitmanip
Working draft of the proposed RISC-V Bitmanipulation extension
neelgala/riscv-config
RISC-V Configuration Validator
neelgala/riscv-crypto
RISC-V cryptography extensions standardisation work.
neelgala/riscv-ctg
neelgala/riscv-elf-psabi-doc
A RISC-V ELF psABI Document
neelgala/riscv-isa-manual
RISC-V Instruction Set Manual
neelgala/riscv-isa-sim
Spike, a RISC-V ISA Simulator
neelgala/riscv-plic-spec
PLIC Specification
neelgala/riscv-tests
neelgala/riscv-v-spec
Working draft of the proposed RISC-V V vector extension
neelgala/rocket-chip
Rocket Chip Generator
neelgala/swerv_eh1
A directory of Western Digital’s RISC-V SweRV Cores
neelgala/test-config
neelgala/testing