Pinned Repositories
AutoSA
AutoSA: Polyhedral-Based Systolic Array Compiler
DSP_coursera
kvm-pcie
Installing KVM and passthrough PCIe (Xilinx FPGA AU200)
matlab-5GNR
Matlab implementations of several 5G L1 functions
rocket-chip
Rocket Chip Generator
Rosebud
Framework for FPGA-accelerated Middlebox Development
rru_8t8r_ad9026
5G RRU reference design - 8T8R using 2 ADI ADRV9026s, FPGA XZCU15EG
SDSoC
Including tutorial and projects
soc-riscv-bd
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
sv-practice
Labs to pratice digital design with System Verilog
nguyencanhtrung's Repositories
nguyencanhtrung/matlab-5GNR
Matlab implementations of several 5G L1 functions
nguyencanhtrung/rru_8t8r_ad9026
5G RRU reference design - 8T8R using 2 ADI ADRV9026s, FPGA XZCU15EG
nguyencanhtrung/kvm-pcie
Installing KVM and passthrough PCIe (Xilinx FPGA AU200)
nguyencanhtrung/sv-practice
Labs to pratice digital design with System Verilog
nguyencanhtrung/AutoSA
AutoSA: Polyhedral-Based Systolic Array Compiler
nguyencanhtrung/Dynamic-Function-eXchange
Guide to get familiar with DFX flow
nguyencanhtrung/firesim
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
nguyencanhtrung/rocket-chip
Rocket Chip Generator
nguyencanhtrung/Rosebud
Framework for FPGA-accelerated Middlebox Development
nguyencanhtrung/soc-riscv-bd
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
nguyencanhtrung/axi-pcie-core
Slaclab PCIe implementation
nguyencanhtrung/bluespec-compiler
Bluespec Compiler (BSC)
nguyencanhtrung/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
nguyencanhtrung/cocotb
Studying cocotb
nguyencanhtrung/FEC
FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)
nguyencanhtrung/fpga-orchard
TBD
nguyencanhtrung/learn-riscv
Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
nguyencanhtrung/litex
Build your hardware, easily!
nguyencanhtrung/MIPS-pipelined
Implementation of a 16-bit pipeline CPU
nguyencanhtrung/nguyencanhtrung.github.io
nguyencanhtrung/noc-constellation
A Chisel RTL generator for network-on-chip interconnects
nguyencanhtrung/ruckus
Vivado build system
nguyencanhtrung/surf
A huge VHDL library for FPGA development
nguyencanhtrung/sus-compiler
A new Hardware Design Language that keeps you in the driver's seat
nguyencanhtrung/sv-axis
AXI4-Stream basic building blocks in SystemVerilog
nguyencanhtrung/sv-common
SystemVerilog Packages for RTL design and verification
nguyencanhtrung/tapa
TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerators.
nguyencanhtrung/vim-beginner
Getting Started with Vim
nguyencanhtrung/website_tmpl
A beautiful, simple, clean, and responsive Jekyll theme for academics
nguyencanhtrung/wol-courses