❗ Important Note |
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This project demonstrates open source eFPGA generated by FABulous. This version is to support wishbone interface with updated DSP tiles. The design was implemented in Sky130nm using OpenLane flow. |
nguyendao-uom/FABulous_eFPGA_wb
FABulous eFPGA with wishbone interface (gg-mpw7-2022)
VerilogApache-2.0