This is the open source tool which is used to create the System Verilog RTL code of register module.
IT STILL DEVELOPING and NOT FINISHED NOW.
doc : Specification documents
input : Configuration file of RegRTLGen
lib : library files
|-- rtl : RTL library
|-- python : Python library
output: RTL and document specification are created by RegRTLGen
work : Working folder contains the main script
cd work
./RegRTLGen.py ../input/RegSpec_Org.xlsx (Python 3.8 or later)
cd ../ouput/ExampleCsr_uvm/sim
./run_qsim.pl (run the default DUT)
./run_qsim.pl -help (show all options)
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