nhan2nguyen

nhan2nguyen's Stars

• amradel2020/vlsi_linkedin_index

  This repo provide an index of VLSI content creators and their materials

  13417

• sharkdp/fd

  A simple, fast and user-friendly alternative to 'find'

  Language:Rust33.8k808

• geekan/HowToLiveLonger

  程序员延寿指南 | A programmer's guide to live longer

  29.9k2.1k

• 4get/uvm_book_examples

  UVM Book Examples - A Practical Guide to Adopting the Universal Verification Methodology (UVM) Second Edition

  Language:Shell2823

• Asabeneh/30-Days-Of-Python

  30 days of Python programming challenge is a step-by-step guide to learn the Python programming language in 30 days. This challenge may take more than100 days, follow your own pace. These videos may help too: https://www.youtube.com/channel/UC7PNRuno1rzYPb1xLa4yktw

  Language:Python42.1k8k

• merldsu/PY_UVM_Framework

  This repo contain the PY-UVM Framework for different RISC-V Cores

  Language:Python31

• naragece/uvm-testbench-tutorial-simple-adder

  A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology

  9387

• waviousllc/wav-lpddr-hw

  Wavious DDR (WDDR) Physical interface (PHY) Hardware

  Language:SystemVerilog9837

• ehmatthes/pcc_2e

  Online resources for Python Crash Course (Second Edition), from No Starch Press

  Language:HTML2.4k1.5k

• vim-python/python-syntax

  Python syntax highlighting for Vim

  Language:Vim script43783

• vinta/awesome-python

  An opinionated list of awesome Python frameworks, libraries, software and resources.

  Language:Python222k24.9k

• bfrg/vim-c-cpp-modern

  Extended Vim syntax highlighting for C and C++ (C++11/14/17/20/23)

  Language:Vim Script56237

• syntacore/scr1

  SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  Language:SystemVerilog853275

• raulbehl/100DaysOfRTL

  100 Days of RTL

  Language:SystemVerilog33097

• dipakkr/A-to-Z-Resources-for-Students

  ✅ Curated list of resources for college students

  17.5k4.5k

• Evensgn/RISC-V-CPU

  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

  Language:Verilog22438

• phatjkk/SpeakIt_Vietnamese_TTS

  Vietnamese Text-to-Speech on Windows Project (zalo-speech)

  Language:C#10144

• nguyenquanicd/SystemCScpuCA

  This is the example of Cycle Accurate (CA) model. It is the Simple CPU (SCPU) is described in SystemC language.

  Language:C++63

• eliukblau/pixterm

  Draw images in your ANSI terminal with true color

  Language:Go96954

• HafsaParker/SingleCycleCPU-RISC-V

  2

• Khadija411/RV32I-Logisim

  8

• nhan2nguyen/2ret-vim

  My personal vim distribution

  1

• vazeri/Embedded-Engineering-RoadMap-2018

  RoadMap to becoming an embedded systems engineer in 2018

  27737

• huongnguyenvan/react-native

  Hướng dẫn học React-Native cho người mới bắt đầu, nếu bạn thấy ổn thì cho star nhé.

  Language:JavaScript27586