This repo aims to document the host interface of the SMSC MEC5035 Embedded Controller (EC) found on the Dell Latitude E6400, a 14" laptop from 2008. The goal of this work is to enable coreboot support for this EC and laptop. Other ECs on Dell Latitude's may also have similar interfaces, such as the MEC5055 on the Latitude E7240
These were found by sniffing the Low Pin Count (LPC) bus between the host and the EC using an FPGA. (TODO: publish FPGA HDL) These dumps are included in this repo. Each line represents a single bus transaction, with each character being a hex digit representing the value of the 4 LAD signals of the bus during a single clock cycle. The final nibble during the last turnaround (TAR) cycle was not included for simplicity of the FPGA design and instead replaced with the newlines. These files were parsed and processed using the various scripts found in the scripts/ directory to make them more human readable and group common access patterns.
No information in this repo will be derived through disassembly, decompilation, or otherwise direct analysis of the EC firmware or system BIOS.
By dumping the bus after carefully chosen events (such as with and without a certain BIOS setup option set) and comparing the processed dumps, any differences that show up likely correlate to the events chosen. This can generally be tested with userspace code writing to the IO ports found in the dumps.