nishit0072e
VLSI || EMBEDDED SYSTEMS || COMPUTER ARCHITECTURE || DIGITAL ELECTRONICS
Dr. B.C. Roy Engineering CollegeDurgapur, West Bengal, India
Pinned Repositories
100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
100DaysOfRtlDesign
I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
16-bit-processor
Processor code, assembly code to noise filter and downsample an image, Instruction Set Architecture files available
2_in_1_bot
A 2 in 1 robot able run on Bluetooth communication and able to avoid obstacle on it's own powered by "Vega processor" which is made in India indigenously by CDAC India
AES_in_verilog
An algorithmic state machine verilog code for AES Encryption/Decryption Algorithm
Calculator
Enc_Dec_Xor
8:3 Encoder is used as input and 3:8 decoder is used as output, to verify that the input and output data are same a Xor gate is implemented, it will return 1 if any mismatch in the input and output data and will 0 if all the bits of input and output match.
RTL-to-GDSII
Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout generation
sev_seg_FPGA
its a seven segment display controller in FPGA which counts in ascending order
WIFI_CAR
A code to operate a battery operated car over wifi control
nishit0072e's Repositories
nishit0072e/RTL-to-GDSII
Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout generation
nishit0072e/100DaysOfRtlDesign
I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
nishit0072e/100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
nishit0072e/2_in_1_bot
A 2 in 1 robot able run on Bluetooth communication and able to avoid obstacle on it's own powered by "Vega processor" which is made in India indigenously by CDAC India
nishit0072e/Enc_Dec_Xor
8:3 Encoder is used as input and 3:8 decoder is used as output, to verify that the input and output data are same a Xor gate is implemented, it will return 1 if any mismatch in the input and output data and will 0 if all the bits of input and output match.
nishit0072e/2bit-Comparator
2 bit comparator design in transistor level in eSim software foremerly FreeCAD
nishit0072e/32-Verilog-Mini-Projects
nishit0072e/Bin_2_BCD
Binary input BCD output in onboard 7-segment display of basys3
nishit0072e/BIN_DEC
nishit0072e/Bin_to_DEC_in_SEV_SEG
nishit0072e/binary
nishit0072e/Cisco_Projects
A simple office Networking demo has been implemented using Cisco Packet Tracer to understand the networking topologies and working of corporate networks between machine to machine.
nishit0072e/Device-Driver
nishit0072e/Embedded_Systems_ST_Projects
"Exploring Creative Solutions with an Arduino Microcontroller: From Beginner to Advanced Projects"
nishit0072e/eSim-Cloud
A web-based system for designing and simulating electronic (eSim) and Arduino circuits.
nishit0072e/nishit0072e
Config files for my GitHub profile.
nishit0072e/Object-Detection-Using-ESP32-CAM-Edge-Impulse-along-with-the-I2C-OLED-Display
Just an example program for combining the OLED Display with Edge Impulse's Arduino Library Code.
nishit0072e/openlane-flow
Openlane is a complete RTL-to-GDS flow, which uses openroad for floorplan, placement etc.
nishit0072e/Register_PIPO_PISO
Parallel in Parallel out, Parallel in Serial out Register Implementation with expansion Capabilities
nishit0072e/RFID-Toll-Gate
A RFID Based Toll gate system is built using Aries v3 development board mounted with Vega Processor, Designed & Developed by CDAC INDIA
nishit0072e/RTL-Coding
"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
nishit0072e/RTL_Design
nishit0072e/sev_seg_rev_FPGA
A VERILOG code on seven segment display controller which counts in descending order
nishit0072e/ssh
nishit0072e/TCP-Calculator
A local server based TCP Calculator
nishit0072e/tt09-verilog-template
Submission template for Tiny Tapeout 9 - Verilog HDL Projects
nishit0072e/Vegetable_Detection
About An AI model has been implemented to detect potato, onion & tomato on a resource constrained hardware
nishit0072e/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
nishit0072e/VLSI-Fundamentals-A-Practical-Approach-Education-Kit
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor
nishit0072e/YT_Digital_series