/ESL

Appendix

Please refer to the PDF document ESL_Response.pdf for detailed descriptions of the derivations used in the paper.

Cache Based Side Channel Attacks

This section presents a curated list of papers in the field of side channel attacks, countermeasures and counterattacks.

References

Side Channel Attacks

  1. Gruss, D., Spreitzer, R., & Mangard, S. (2015). Cache Template Attacks: Automating Attacks on Inclusive {Last-Level} Caches. In 24th USENIX Security Symposium (USENIX Security 15) (pp. 897-912). Link
  2. Osvik, D. A., Shamir, A., & Tromer, E. (2006, February). Cache attacks and countermeasures: the case of AES. In Cryptographers’ track at the RSA conference (pp. 1-20). Springer, Berlin, Heidelberg. Link
  3. Neve, M., & Seifert, J. P. (2006, August). Advances on access-driven cache attacks on AES. In International Workshop on Selected Areas in Cryptography (pp. 147-162). Springer, Berlin, Heidelberg. Link
  4. Gullasch, D., Bangerter, E., & Krenn, S. (2011, May). Cache games--bringing access-based cache attacks on AES to practice. In 2011 IEEE Symposium on Security and Privacy (pp. 490-505). IEEE. Link
  5. Gruss, D., Maurice, C., Wagner, K., & Mangard, S. (2016, July). Flush+ Flush: a fast and stealthy cache attack. In International Conference on Detection of Intrusions and Malware, and Vulnerability Assessment (pp. 279-299). Springer, Cham. Link
  6. Wang, D., Qian, Z., Abu-Ghazaleh, N., & Krishnamurthy, S. V. (2019, June). Papp: Prefetcher-aware prime and probe side-channel attack. In Proceedings of the 56th Annual Design Automation Conference 2019 (pp. 1-6). Link
  7. Liu, F., Yarom, Y., Ge, Q., Heiser, G., & Lee, R. B. (2015, May). Last-level cache side-channel attacks are practical. In 2015 IEEE symposium on security and privacy (pp. 605-622). IEEE. Link
  8. Yarom, Y., & Falkner, K. (2014). {FLUSH+ RELOAD}: A High Resolution, Low Noise, L3 Cache {Side-Channel} Attack. In 23rd USENIX security symposium (USENIX security 14) (pp. 719-732). Link
  9. Saxena, A., & Panda, B. (2020). DABANGG: time for fearless flush based cache attacks. Cryptology ePrint Archive. Link
  10. Didier, G., & Maurice, C. (2021, July). Calibration Done Right: Noiseless Flush+ Flush Attacks. In International Conference on Detection of Intrusions and Malware, and Vulnerability Assessment (pp. 278-298). Springer, Cham. Link
  11. Mukhtar, M. A., Mushtaq, M., Bhatti, M. K., Lapotre, V., & Gogniat, G. (2020). Flush+ prefetch: A countermeasure against access-driven cache-based side-channel attacks. Journal of Systems Architecture, 104, 101698. Link
  12. Jayasinghe, D., Fernando, J., Herath, R., & Ragel, R. (2010, December). Remote cache timing attack on advanced encryption standard and countermeasures. In 2010 Fifth International Conference on Information and Automation for Sustainability (pp. 177-182). IEEE. Link
  13. Spreitzer, R., & Plos, T. (2013, March). Cache-access pattern attack on disaligned aes t-tables. In International Workshop on Constructive Side-Channel Analysis and Secure Design (pp. 200-214). Springer, Berlin, Heidelberg. Link
  14. Yan, M., Fletcher, C. W., & Torrellas, J. (2020). Cache telepathy: Leveraging shared resource attacks to learn {DNN} architectures. In 29th USENIX Security Symposium (USENIX Security 20) (pp. 2003-2020). Link
  15. Liu, Y., & Srivastava, A. (2020, November). Ganred: Gan-based reverse engineering of dnns via cache side-channel. In Proceedings of the 2020 ACM SIGSAC Conference on Cloud Computing Security Workshop (pp. 41-52).Link
  16. Hua, W., Zhang, Z., & Suh, G. E. (2022). Reverse Engineering CNN Models using Side-Channel Attacks. IEEE Design & Test. Link
  17. Yan, M., Sprabery, R., Gopireddy, B., Fletcher, C., Campbell, R., & Torrellas, J. (2019, May). Attack directories, not caches: Side channel attacks in a non-inclusive world. In 2019 IEEE Symposium on Security and Privacy (SP) (pp. 888-904). IEEE. Link

Countermeasures and Counterattacks

  1. Martin, R., Demme, J., & Sethumadhavan, S. (2012, June). Timewarp: Rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks. In 2012 39th Annual International Symposium on Computer Architecture (ISCA) (pp. 118-129). IEEE. Link
  2. Page, D. (2005). Partitioned cache architecture as a side-channel defence mechanism. Cryptology ePrint Archive. Link
  3. Vattikonda, B. C., Das, S., & Shacham, H. (2011, October). Eliminating fine grained timers in Xen. In Proceedings of the 3rd ACM workshop on Cloud computing security workshop (pp. 41-46). Link
  4. Dhavlle, A., Mehta, R., Rafatirad, S., Homayoun, H., & Dinakarrao, S. M. P. (2020, March). Entropy-shield: Side-channel entropy maximization for timing-based side-channel attacks. In 2020 21st International Symposium on Quality Electronic Design (ISQED) (pp. 161-166). IEEE. Link
  5. Qureshi, M. K. (2019, June). New attacks and defense for encrypted-address cache. In 2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA) (pp. 360-371). IEEE. Link
  6. Werner, M., Unterluggauer, T., Giner, L., Schwarz, M., Gruss, D., & Mangard, S. (2019). {ScatterCache}: Thwarting Cache Attacks via Cache Set Randomization. In 28th USENIX Security Symposium (USENIX Security 19) (pp. 675-692). Link
  7. Wang, H., Sayadi, H., Mohsenin, T., Zhao, L., Sasan, A., Rafatirad, S., & Homayoun, H. (2020, March). Mitigating cache-based side-channel attacks through randomization: A comprehensive system and architecture level analysis. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 1414-1419). IEEE. Link
  8. Liu, F., & Lee, R. B. (2014, December). Random fill cache architecture. In 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 203-215). IEEE.Link
  9. Song, W., Li, B., Xue, Z., Li, Z., Wang, W., & Liu, P. (2021, May). Randomized last-level caches are still vulnerable to cache side-channel attacks! But we can fix it. In 2021 IEEE Symposium on Security and Privacy (SP) (pp. 955-969). IEEE. Link
  10. Bodduna, R., Ganesan, V., Slpsk, P., Veezhinathan, K., & Rebeiro, C. (2020). Brutus: Refuting the security claims of the cache timing randomization countermeasure proposed in ceaser. IEEE Computer Architecture Letters, 19(1), 9-12. Link
  11. Bhattacharya, S., Rebeiro, C., & Mukhopadhyay, D. (2013, June). Unraveling timewarp: What all the fuzz is about?. In Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy (pp. 1-8). Link
  12. Zhang, Y., & Reiter, M. K. (2013, November). Düppel: Retrofitting commodity operating systems to mitigate cache side channels in the cloud. In Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security (pp. 827-838). Link
  13. Sanchez, D., & Kozyrakis, C. (2010, December). The ZCache: Decoupling ways and associativity. In 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture (pp. 187-198). IEEE. Link
  14. Page, D. (2005). Partitioned cache architecture as a side-channel defence mechanism. Cryptology ePrint Archive. Link
  15. Jaamoum, A., Hiscock, T., & Di Natale, G. (2021, February). Scramble cache: An efficient cache architecture for randomized set permutation. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 621-626). IEEE. Link
  16. Page, D. (2003). Defending against cache-based side-channel attacks. Information Security Technical Report, 8(1), 30-44. Link
  17. Kiriansky, V., Lebedev, I., Amarasinghe, S., Devadas, S., & Emer, J. (2018, October). DAWG: A defense against cache timing attacks in speculative execution processors. In 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (pp. 974-987). IEEE. Link
  18. Mushtaq, M., Akram, A., Bhatti, M. K., Chaudhry, M., Lapotre, V., & Gogniat, G. (2018, June). Nights-watch: A cache-based side-channel intrusion detector using hardware performance counters. In Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy (pp. 1-8).Link
  19. Mushtaq, M., Akram, A., Bhatti, M. K., Rais, R. N. B., Lapotre, V., & Gogniat, G. (2018, October). Run-time detection of prime+ probe side-channel attack on AES encryption algorithm. In 2018 Global Information Infrastructure and Networking Symposium (GIIS) (pp. 1-5). IEEE. Link
  20. Mushtaq, M., Bricq, J., Bhatti, M. K., Akram, A., Lapotre, V., Gogniat, G., & Benoit, P. (2020). WHISPER: A tool for run-time detection of side-channel attacks. IEEE Access, 8, 83871-83900. Link
  21. Mushtaq, M., Akram, A., Bhatti, M. K., Chaudhry, M., Yousaf, M., Farooq, U., & Gogniat, G. (2018, December). Machine learning for security: The case of side-channel attack detection at run-time. In 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (pp. 485-488). IEEE. Link
  22. Mushtaq, M., Akram, A., Bhatti, M. K., Lapotre, V., & Gogniat, G. (2018, June). Cache-Based Side-Channel Intrusion Detection using Hardware Performance Counters. In CryptArchi 2018-16th International Workshops on Cryptographic architectures embedded in logic devices. Link
  23. Kong, J., Aciiçmez, O., Seifert, J. P., & Zhou, H. (2009, February). Hardware-software integrated approaches to defend against software cache-based side channel attacks. In 2009 IEEE 15th international symposium on high performance computer architecture (pp. 393-404). IEEE. Link
  24. Kim, T., Peinado, M., & Mainar-Ruiz, G. (2012). {STEALTHMEM}:{System-Level} Protection Against {Cache-Based} Side Channel Attacks in the Cloud. In 21st USENIX Security Symposium (USENIX Security 12) (pp. 189-204). Link
  25. Kong, J., Aciicmez, O., Seifert, J. P., & Zhou, H. (2008, October). Deconstructing new cache designs for thwarting software cache-based side channel attacks. In Proceedings of the 2nd ACM workshop on Computer security architectures (pp. 25-34). Link
  26. Lv, Z., Zhao, Y., & Zhang, C. (2020, June). DegradeTimer: Mitigating Dedicated Thread Timer based Microarchitectural Timing Channels. In ICC 2020-2020 IEEE International Conference on Communications (ICC) (pp. 1-7). IEEE. Link
  27. Cao, Y., Chen, Z., Li, S., & Wu, S. (2017, October). Deterministic browser. In Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security (pp. 163-178). Link
  28. Hu, W. M. (1992). Reducing timing channels with fuzzy time. Journal of computer security, 1(3-4), 233-254. Link
  29. Kohlbrenner, D., & Shacham, H. (2016). Trusted browsers for uncertain times. In 25th USENIX Security Symposium (USENIX Security 16) (pp. 463-480). Link
  30. Sabbagh, M., Fei, Y., Wahl, T., & Ding, A. A. (2018, November). Scadet: A side-channel attack detection tool for tracking prime-probe. In 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (pp. 1-8). ACM. Link
  31. Wang, H., Sayadi, H., Sasan, A., Rafatirad, S., & Homayoun, H. (2020, December). Hybridg: Hybrid dynamic time warping and gaussian distribution model for detecting emerging zero-day microarchitectural side-channel attacks. In 2020 19th IEEE International Conference on Machine Learning and Applications (ICMLA) (pp. 604-611). IEEE.Link
  32. Sangeetha, G., & Sumathi, G. (2021). An optimistic technique to detect Cache based Side Channel attacks in Cloud. Peer-to-Peer Networking and Applications, 14(4), 2473-2486. Link
  33. Cho, J., Kim, T., Kim, S., Im, M., Kim, T., & Shin, Y. (2020). Real-time detection for cache side channel attack using performance counter monitor. Applied Sciences, 10(3), 984. Link
  34. Bhade, P. P., & Sinha, S. (2021, December). Detection of Cache Side Channel Attacks Using Thread Level Monitoring of Hardware Performance Counters. In 2021 IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) (pp. 210-217). IEEE. Link
  35. Bazm, M. M., Sautereau, T., Lacoste, M., Sudholt, M., & Menaud, J. M. (2018, April). Cache-based side-channel attacks detection through intel cache monitoring technology and hardware performance counters. In 2018 Third International Conference on Fog and Mobile Edge Computing (FMEC) (pp. 7-12). IEEE. Link
  36. Gulmezoglu, B., Moghimi, A., Eisenbarth, T., & Sunar, B. (2019). Fortuneteller: Predicting microarchitectural attacks via unsupervised deep learning. arXiv preprint arXiv:1907.03651. Link
  37. Vasilikos, P., Nielson, H. R., Nielson, F., & Köpf, B. (2019, June). Timing leaks and coarse-grained clocks. In 2019 IEEE 32nd Computer Security Foundations Symposium (CSF) (pp. 32-3215). IEEE. Link
  38. Wang, Z., Peng, S., Guo, X., & Jiang, W. (2018, November). Zero in and TimeFuzz: detection and mitigation of cache side-channel attacks. In International Conference on Security for Information Technology and Communications (pp. 410-424). Springer, Cham. Link
  39. Saileshwar, G., & Qureshi, M. (2021). {MIRAGE}: Mitigating {Conflict-Based} Cache Attacks with a Practical {Fully-Associative} Design. In 30th USENIX Security Symposium (USENIX Security 21) (pp. 1379-1396). Link
  40. Yan, M., Gopireddy, B., Shull, T., & Torrellas, J. (2017, June). Secure hierarchy-aware cache replacement policy (SHARP): Defending against cache-based side channel attacks. In 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA) (pp. 347-360). IEEE. Link
  41. Zhang, T., Zhang, Y., & Lee, R. B. (2016, September). Cloudradar: A real-time side-channel attack detection system in clouds. In International Symposium on Research in Attacks, Intrusions, and Defenses (pp. 118-140). Springer, Cham. Link
  42. Percival, C. (2005). Cache missing for fun and profit. Link
  43. Enomoto, S., & Kuzuno, H. (2021, September). FlushBlocker: Lightweight mitigating mechanism for CPU cache flush instruction based attacks. In 2021 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW) (pp. 74-79). IEEE. Link
  44. Qureshi, M. K. (2018, October). CEASER: Mitigating conflict-based cache attacks via encrypted-address and remapping. In 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (pp. 775-787). IEEE. Link
  45. Dhavlle, A., Mehta, R., Rafatirad, S., Homayoun, H., & Dinakarrao, S. M. P. (2020, March). Entropy-shield: Side-channel entropy maximization for timing-based side-channel attacks. In 2020 21st International Symposium on Quality Electronic Design (ISQED) (pp. 161-166). IEEE. Link
  46. Crane, S., Homescu, A., Brunthaler, S., Larsen, P., & Franz, M. (2015, February). Thwarting cache side-channel attacks through dynamic software diversity. In NDSS (pp. 8-11).Link
  47. Chabanne, H., Danger, J. L., Guiga, L., & Kühne, U. (2021). Side channel attacks for architecture extraction of neural networks. CAAI Transactions on Intelligence Technology, 6(1), 3-16.Link
  48. Mi, Z., Chen, H., Zhang, Y., Peng, S., Wang, X., & Reiter, M. K. (2018). Cpu elasticity to mitigate cross-vm runtime monitoring. IEEE Transactions on Dependable and Secure Computing, 17(5), 1094-1108.Link
  49. Wang, H., Sayadi, H., Sasan, A., Rafatirad, S., & Homayoun, H. (2020, November). Hybrid-shield: Accurate and efficient cross-layer countermeasure for run-time detection and mitigation of cache-based side-channel attacks. In Proceedings of the 39th International Conference on Computer-Aided Design (pp. 1-9). Link
  50. Wang, H., Sayadi, H., Mohsenin, T., Zhao, L., Sasan, A., Rafatirad, S., & Homayoun, H. (2020, March). Mitigating cache-based side-channel attacks through randomization: A comprehensive system and architecture level analysis. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 1414-1419). IEEE. Link
  51. Liu, F., Wu, H., Mai, K., & Lee, R. B. (2016). Newcache: Secure cache architecture thwarting cache side-channel attacks. IEEE Micro, 36(5), 8-16. Link
  52. Liu, F., Ge, Q., Yarom, Y., Mckeen, F., Rozas, C., Heiser, G., & Lee, R. B. (2016, March). Catalyst: Defeating last-level cache side channel attacks in cloud computing. In 2016 IEEE international symposium on high performance computer architecture (HPCA) (pp. 406-418). IEEE. Link

Survey Papers

  1. Ge, Q., Yarom, Y., Cock, D., & Heiser, G. (2018). A survey of microarchitectural timing attacks and countermeasures on contemporary hardware. Journal of Cryptographic Engineering, 8(1), 1-27. Link
  2. Randolph, M., & Diehl, W. (2020). Power side-channel attack analysis: A review of 20 years of study for the layman. Cryptography, 4(2), 15. Link
  3. Lyu, Y., & Mishra, P. (2018). A survey of side-channel attacks on caches and countermeasures. Journal of Hardware and Systems Security, 2(1), 33-50. Link
  4. Mushtaq, M., Mukhtar, M. A., Lapotre, V., Bhatti, M. K., & Gogniat, G. (2020). Winter is here! A decade of cache-based side-channel attacks, detection & mitigation for RSA. Information Systems, 92, 101524. Link
  5. Lou, X., Zhang, T., Jiang, J., & Zhang, Y. (2021). A survey of microarchitectural side-channel vulnerabilities, attacks, and defenses in cryptography. ACM Computing Surveys (CSUR), 54(6), 1-37. Link
  6. Akram, A., Mushtaq, M., Bhatti, M. K., Lapotre, V., & Gogniat, G. (2020). Meet the Sherlock Holmes’ of side channel leakage: A survey of cache SCA detection techniques. IEEE Access, 8, 70836-70860. Link49.
  7. Mushtaq, M., Akram, A., Bhatti, M. K., Ali, U., Lapotre, V., & Gogniat, G. (2019, June). Sherlock Holmes of Cache Side-Channel Attacks in Intel's x86 Architecture. In 2019 IEEE Conference on Communications and Network Security (CNS) (pp. 1-9). IEEE. Link
  8. Hettwer, B., Gehrer, S., & Güneysu, T. (2020). Applications of machine learning techniques in side-channel attacks: a survey. Journal of Cryptographic Engineering, 10(2), 135-162. Link
  9. Su, C., & Zeng, Q. (2021). Survey of CPU cache-based side-channel attacks: systematic analysis, security models, and countermeasures. Security and Communication Networks, 2021. Link
  10. Shen, C., Chen, C., & Zhang, J. (2021, January). Micro-architectural cache side-channel attacks and countermeasures. In 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) (pp. 441-448). IEEE.Link

Theoritical Analysis

  1. de Chérisey, E., Guilley, S., Rioul, O., & Piantanida, P. (2019). Best information is most successful. Cryptology ePrint Archive. Link
  2. De Cherisey, E., Guilley, S., Rioul, O., & Piantanida, P. (2019, July). An information-theoretic model for side-channel attacks in embedded hardware. In 2019 IEEE International Symposium on Information Theory (ISIT) (pp. 310-315). IEEE. Link
  3. Cheng, W., Liu, Y., Guilley, S., & Rioul, O. (2021). Attacking masked cryptographic implementations: Information-theoretic bounds. arXiv preprint arXiv:2105.07436. Link
  4. Ito, A., Ueno, R., & Homma, N. (2022). On the Success Rate of Side-Channel Attacks on Masked Implementations: Information-Theoretical Bounds and Their Practical Usage. Cryptology ePrint Archive. Link
  5. Mao, B., Hu, W., Althoff, A., Matai, J., Oberg, J., Mu, D., & Kastner, R. (2015, November). Quantifying timing-based information flow in cryptographic hardware. In 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (pp. 552-559). IEEE. Link
  6. Yang, W., & Zhang, H. (2019, December). Side-channel leakage amount estimation based on communication theory. In 2019 IEEE Global Communications Conference (GLOBECOM) (pp. 1-6). IEEE.Link
  7. Guo, Q., Grosso, V., Standaert, F. X., & Bronchain, O. (2020). Modeling soft analytical side-channel attacks from a coding theory viewpoint. IACR Transactions on Cryptographic Hardware and Embedded Systems, 209-238. Link
  8. Gierlichs, B., Batina, L., & Tuyls, P. (2007). Mutual information analysis--a universal differential side-channel attack. Cryptology ePrint Archive.Link
  9. Ou, C., Zhou, X., Lam, S. K., Zhou, C., & Ning, F. (2020). Information Entropy-Based Leakage Profiling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 40(6), 1052-1062. Link
  10. Richter, B., Knichel, D., & Moradi, A. (2019, November). A Comparison of $\chi^ 2$-Test and Mutual Information as Distinguisher for Side-Channel Analysis. In International Conference on Smart Card Research and Advanced Applications (pp. 237-251). Springer, Cham. Link
  11. Duc, A., Dziembowski, S., & Faust, S. (2014, May). Unifying leakage models: from probing attacks to noisy leakage. In Annual International Conference on the Theory and Applications of Cryptographic Techniques (pp. 423-440). Springer, Berlin, Heidelberg.Link
  12. Fei, Y., Ding, A. A., Lao, J., & Zhang, L. (2014). A statistics-based fundamental model for side-channel attack analysis. Cryptology ePrint Archive. Link
  13. Tănăsescu, A., Choudary, M. O., Rioul, O., & Popescu, P. G. (2021). Asymptotically Optimal Massey-Like Inequality on Guessing Entropy With Application to Side-Channel Attack Evaluations. arXiv preprint arXiv:2103.15620. Link
  14. Cheng, W., Rioul, O., & Guilley, S. (2019, April). Guessing a secret cryptographic key from side-channel leakages. In 2019 IEEE European School of Information Theory (ESIT'19).Link
  15. Zhang, D., Zhou, C., Li, S., Yu, D., & He, K. (2020). Evaluation of Information Leakage of Cryptographic Chip Based on Variance. IEEE Letters on Electromagnetic Compatibility Practice and Applications, 2(4), 174-177.Link
  16. Vila, P., Köpf, B., & Morales, J. F. (2019, May). Theory and practice of finding eviction sets. In 2019 IEEE Symposium on Security and Privacy (SP) (pp. 39-54). IEEE. Link
  17. Song, W., & Liu, P. (2019). Dynamically Finding Minimal Eviction Sets Can Be Quicker Than You Think for {Side-Channel} Attacks against the {LLC}. In 22nd International Symposium on Research in Attacks, Intrusions and Defenses (RAID 2019) (pp. 427-442).Link
  18. He, Z., & Lee, R. B. (2017, October). How secure is your cache against side-channel attacks?. In Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 341-353).Link
  19. Yarom, Y. (2016). Mastik: A micro-architectural side-channel toolkit. Link
  20. Alam, M., & Mukhopadhyay, D. (2019, June). How secure are deep learning algorithms from side-channel based reverse engineering?. In Proceedings of the 56th Annual Design Automation Conference 2019 (pp. 1-2). Link
  21. Hong, S., Davinroy, M., Kaya, Y., Locke, S. N., Rackow, I., Kulda, K., ... & Dumitraş, T. (2018). Security analysis of deep neural networks operating in the presence of cache side-channel attacks. arXiv preprint arXiv:1810.03487. Link

Useful Code Repositories

  1. Flush+Reload
  2. Cache based side channel attacks
  3. https://gist.github.com/ErikAugust/724d4a969fb2c6ae1bbd7b2a9e3d4bb6
  4. Dabangg
  5. Reload+Refresh