Mapping Equivalence Checking
Technology mapping is an essential step in EDA
flow. However, the function of the circuit may be changed after
technology mapping, and equivalence checking (EC) based
verification is highly necessary. The traditional EC method
has significant time and resource constraints, making it only
feasible to carry out at a coarse-grained level. To make it
efficient for technology mapping, we propose a fine-grained
method called MEC, which leverages a combination of two
approaches to significantly reduce the time cost of verification.
The local block verification approach performs fast verification
and the global graph cover approach guarantees correctness.
The proposed method is rigorously tested and compared to
three EC tools, and the results show that MEC technique offers
a substantial improvement in speed. MEC not only offers a
faster and more efficient way of performing EC on technology
mapping but also opens up new opportunities for more fine-
grained verification in the future.
details please refer to MEC