Simple sample project for Cora Z7 07S.
- Ubuntu18.04
- Vivado 2021.1
- Unlicense
mkdir build
cd build
cmake ..
make impl_vivado_study
Output Directory:
build/vivado/vivado_study.prj/vivado_study.runs/impl_1
build/vivado/vivado_study.prj/vivado_study.runs/child_0_impl_1
You can write a bitstream by the following command.
write build/vivado/vivado_study.prj/vivado_study.runs/impl_1/top.bit
make JTAG=<Target Number> program_vivado_study
write build/vivado/vivado_study.prj/vivado_study.runs/impl_1/myrtl_myrtl_partial.bit
make JTAG=<Target Number> program_vivado_study_pr0
write build/vivado/vivado_study.prj/vivado_study.runs/child_0_impl_1/myrtl_myled2_partial.bit
make JTAG=<Target Number> program_vivado_study_pr1
-DVIVADO_ROOT=<Vivado Directory>
: Vivado install directory(exp: C:/Xilinx/Vivado/2021.1)-DVITIS_HLS_ROOT=<Vitis HLS Directory>
: Vitis HLS install directory(exp: C:/Xilinx/Vitis_HLS/2021.1)
xsdb
: run xsdbvivado_study
: Create vivado_study Vivado projectopen_vivado_study
: Open vivado_study projectclear_vivado_study
: Delete vivado_study Vivado projectimpl_vivado_study
: Generate a bitstreamprogram_vivado_study
: Write a bitstream to FPGA (use xsdb)export_bd_vivado_study
: Export design file (vivado/design_1.tcl)report_addr_vivado_study
: Report addresscreate_project_hlsled
: Create hlsled Vitis HLS projectopen_hlsled
: Open hlsled projectclear_hlsled
: Delete hlsled Vitis HLS projectbuild_test_hlsled
: Compile C++ Test of hlsled (* You can run this test usingctest
)test_hlsled
: Runbuild_test_hlsled
productscsynth_hlsled
: Perform high-level synthesis of hlsledcosim_hlsled
: Run C/RTL simulation of hlsled (It don't work)
- src/constraint/ : constraints
- src/rtl/ : Verilog RTL
- vivado/ : vivado project
- cmake/ : cmake codes
build/vivado/dfx/vivado_study.prj
: Vivado projectbuild/vivado/zynq/zynq_study.prj
: Zynq vivado projectbuild/vivado/zynq/zynq_vitis.prj
: Zynq vitis workspacebuild/src/hls/hlsled/hlsled
: Vitis HLS project