Pinned Repositories
802.15.4
Medium Access Control layer of 802.15.4
amba_sys_ip
AMBA-protocol system IP
automation_test
AutoSVA
AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.
emacs
OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
PSS
PSS Blended Modeling
spinalhdl-online
uvm-sc
UVM SystemC source, with my own additions
verification-userexample
nonamehi's Repositories
nonamehi/verification-userexample
nonamehi/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
nonamehi/PSS
PSS Blended Modeling
nonamehi/spinalhdl-online
nonamehi/AutoSVA
AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.
nonamehi/awesome-hardware-tools
List of awesome open source hardware tools
nonamehi/awesome-hdl
Hardware Description Languages
nonamehi/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
nonamehi/batchRun
batchRun is an ansible-similar IT automation system, which is more suitable for IC industry.
nonamehi/bender
A dependency management tool for hardware projects.
nonamehi/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
nonamehi/coverage
Implementation of post-process coverage, and batch waveform search
nonamehi/draw.io
nonamehi/drawio
Source to app.diagrams.net
nonamehi/fusesoc-cores
FuseSoC standard core library
nonamehi/HDLGen
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
nonamehi/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
nonamehi/ic_flow_platform
IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow contral.
nonamehi/JSONinSV
JSON lib in Systemverilog
nonamehi/noVNC
VNC client web application
nonamehi/pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
nonamehi/pulp-runtime
Simple runtime for Pulp platforms
nonamehi/pulp_cluster
The multi-core cluster of a PULP system.
nonamehi/pysv
Running Python code in SystemVerilog
nonamehi/pyuvm
The UVM written in Python
nonamehi/qemu
Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.
nonamehi/regression_tests
nonamehi/uvm_testbench_gen
Novel GUI Based UVM Testbench Template Builder
nonamehi/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
nonamehi/wb2axip
Bus bridges and other odds and ends