Denise uses wrong clocks

[nonarkitten]

Remove PLL and rely on stock clocks. The original Denise chip has only two clock inputs: 7M and CCK. From this, it's possible to drive a 14MHz event on the positive and negative edges and also generate CCKQ from the XOR of 7M and CCK.

ECS Denise adds the CDAC (quadrature 7M) which allows the creation of a 14MHz clock and 28MHz events which would be required for super hires and productivity (pseudo VGA) modes. I say pseudo here only because VGA is normally 25MHz, not 28MHz.