nonarkitten/amiga_replacement_project
This is an attempt to make clean Verilog sources for each chip on the Amiga.
VerilogNOASSERTION
Issues
- 4
Possibility of a ReAgnus for Amiga 1000
#17 opened by markusbkk - 0
IPL outputs of Paula should be open drain
#16 opened by nretro - 3
ECS agnus schematics
#7 opened by mithrendal - 1
[Question] Scope/extent of the project
#12 opened by ceztko - 3
Missing rev 0.5 schematics
#11 opened by Syntec1 - 5
Images
#6 opened by nonarkitten - 0
Denise does not support genlock
#5 opened by nonarkitten - 0
Denise not reading mice
#4 opened by nonarkitten - 0
Denise uses wrong clocks
#3 opened by nonarkitten