Pinned Repositories
AdderTreeGenerateScript
A python script for generating Parameterizable AdderTree(unsigned) verilog module.
convolution_network_on_FPGA
CNN acceleration on virtex-7 FPGA with verilog HDL
Debounce_zedboard
fpu
synthesiseable ieee 754 floating point library in verilog
Graduation
Graduation_Rectify
kalibr
The Kalibr calibration toolbox
Systolic-Array
course design
Systolic_Array_FIR
Implementation of a FIR filter based on Systolic Array using Verilog
verilog-axis
Verilog AXI stream components
nqHITSZ's Repositories
nqHITSZ/Systolic-Array
course design
nqHITSZ/Systolic_Array_FIR
Implementation of a FIR filter based on Systolic Array using Verilog
nqHITSZ/AdderTreeGenerateScript
A python script for generating Parameterizable AdderTree(unsigned) verilog module.
nqHITSZ/convolution_network_on_FPGA
CNN acceleration on virtex-7 FPGA with verilog HDL
nqHITSZ/fpu
synthesiseable ieee 754 floating point library in verilog
nqHITSZ/verilog-axis
Verilog AXI stream components
nqHITSZ/Debounce_zedboard
nqHITSZ/Graduation
nqHITSZ/Graduation_Rectify
nqHITSZ/kalibr
The Kalibr calibration toolbox
nqHITSZ/no-OS
Software drivers for systems without OS
nqHITSZ/Systolic-Array-1
Systolic array based hardware for Image processing on the SPARTAN-6 FPGA
nqHITSZ/systolic-array-sorting
Implementation of a Systolic Array based sorting engine using Verilog
nqHITSZ/the_gvim_cfg