oktayogutcu

oktayogutcu's Stars

• DPCEKY/systolic-array

  HLS implemented systolic array structure

  Language:C3812

• Xilinx/Vitis-HLS-Introductory-Examples

  Language:C++577157

• AniketBadhan/Convolutional-Neural-Network

  Implementation of CNN using Verilog

  Language:Verilog17575

• xizhengszhang/Leetcode_company_frequency

  Collection of leetcode company tag problems. Periodically updating.

  5.6k1.8k

• cocotb/cocotb

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  Language:Python1.7k502

• alexforencich/cocotbext-axi

  AXI interface modules for Cocotb

  Language:Python20868

• verilog-to-routing/vtr-verilog-to-routing

  Verilog to Routing -- Open Source CAD Flow for FPGA Research

  Language:C++1k386

• YosysHQ/yosys

  Yosys Open SYnthesis Suite

  Language:C++3.4k874

• tpoikela/uvm-python

  UVM 1.2 port to Python

  Language:Python23445

• ben-marshall/awesome-open-hardware-verification

  A List of Free and Open Source Hardware Verification Tools and Frameworks

  47946

• PyHDI/Pyverilog

  Python-based Hardware Design Processing Toolkit for Verilog HDL

  Language:Python615170