This repository contains the Rocket chip generator necessary to instantiate the RISC-V Zscale Core.
- Quick instructions for those who want to dive directly into the details without knowing exactly what's in the repository.
- How should I use the Rocket chip generator?
- How can I parameterize my Rocket chip?
$ git clone https://github.com/onchipuis/zscale.git
$ cd zscale
$ git submodule update --init
$ cd rocket-chip
$ git submodule update --init
To build the rocket-chip repository, you must point the RISCV environment variable to your riscv-tools installation directory.
$ export RISCV=/path/to/riscv/toolchain/installation
The riscv-tools repository is already included in rocket-chip as a git submodule. You must build this version of riscv-tools:
$ cd zscale/rocket-chip/riscv-tools
$ git submodule update --init --recursive
$ export RISCV=/path/to/install/riscv/toolchain
$ export MAKEFLAGS="$MAKEFLAGS -jN" # Assuming you have N cores on your host system
$ ./build.sh
$ ./build-rv32ima.sh (if you are using RV32).
For more information (or if you run into any issues), please consult the riscv-tools/README.
You may need to install some additional packages to use this repository. Rather than list all dependencies here, please see the appropriate section of the READMEs for each of the subprojects:
To build the core in verilog:
$ make
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You can generate synthesizable Verilog with the following commands:
$ make CONFIG=DefaultConfig
You can generate synthesizable Verilog for minimum:
$ make CONFIG=TinyConfig
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You can generate Verilog for your VLSI flow with the following commands:
$ make verilog
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Can be found here.
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