Issues
- 0
Feature Request: Use of a gernic board under yosys
#28 opened by swittlich - 1
- 0
- 3
- 0
Reliable Node Extractor for VHDL/Verilog
#24 opened by HendrikMennen - 0
Associate Log Messages with Projects
#22 opened by HendrikMennen - 0
- 0
VHDL Autoindent broken
#17 opened by HendrikMennen - 0
- 0
Add VSCODE Snippet Variables
#14 opened by HendrikMennen - 1
GIT Support Tasks
#12 opened by HendrikMennen - 1
- 1
SVG generation with one click
#9 opened by std-rubic - 1
ZSH not working correctly in MacOS
#5 opened by HendrikMennen - 1
ReadyToRun breaks terminal on linux
#6 opened by HendrikMennen - 0
Add GHW, FST Parser
#4 opened by HendrikMennen - 0
Design Hierarchy View
#2 opened by std-rubic - 0
Document Outline View
#3 opened by std-rubic