openquantumhardware/qick

Issues

• Custom register doesn't like int32

  #290 opened 2 months ago by i-am-mounce
  4

• Can't read 4x2 metadata with 0.2.287

  #288 opened 3 months ago by i-am-mounce
  5

• Software is no longer compatible with Python 3.6 (PYNQ OS 2.6)

  #284 opened 3 months ago by meeg
  0

• Start time of pulses across multiple DACs misaligned

  #277 opened 4 months ago by danieljamesgraham
  8

• ZCU216 Image fails when running qpsk_overlay

  #278 opened 4 months ago by cplonski20
  1

• ZCU216 image has no static MAC address

  #182 opened a year ago by dangernoodle-dev
  2

• Uable to run pscp to copy qick tool in RFSoC 4x2 Board

  #274 opened 4 months ago by atifjafri
  5

• Do the decimated IQ samples from the ADC have the wrong phase relationship?

  #269 opened 4 months ago by LukeTrainor
  2

• Only 8 out 16 digital pins available.

  #270 opened 5 months ago by ibwharri
  5

• Clarification on intended behaviour of `AveragerProgram.trigger()`

  #153 opened a year ago by Cameron-Spence-Riverlane
  3

• [Errno 6] No such device or address

  #166 opened a year ago by alec-yen
  3

• B_PHASE class attribute missing on AxisSgMux4Vx classes

  #259 opened 8 months ago by dmtvanzanten
  2

• pfb readout phase seems random while sweeping freq

  #251 opened 9 months ago by Ri-chard-Wu
  2

• Unable to reproduce the results with the same ["pulse_gain"] paramter

  #250 opened 9 months ago by flyingdorothia
  1

• change ADC readout port with bitstream

  #213 opened 9 months ago by lisafan122
  3

• Read jump point and error of direct downconversion

  #236 opened 9 months ago by JayChien04717
  2

• Adding a .simulate() to the AveragerProgram class?

  #229 opened 10 months ago by tristanlorriaux
  3

• use a machine learning training algorithm from a different FPGA

  #221 opened a year ago by flyingdorothia
  3

• Read photodetector output -> ADC with the right input power and pulse gain

  #219 opened a year ago by flyingdorothia
  1

• Does the loopback test requires amplifier

  #218 opened a year ago by flyingdorothia
  1

• incomplete files in building new firmwire

  #215 opened a year ago by flyingdorothia
  2

• changed ADC port in tcl but unable to measure meaningful data in readout

  #217 opened a year ago by flyingdorothia
  1

• Unable to load bitstream to FPGA

  #216 opened a year ago by flyingdorothia
  1

• Unable to send a number with DAC and receive a number with ADC in a deterministic manner

  #214 opened a year ago by flyingdorothia
  1

• Unable to build my own firmwire

  #212 opened a year ago by lisafan122
  3

• ADC readouts corrupted with non white noise

  #185 opened a year ago by JavierSerranoGarcia
  3

• Reuse QickSoc object when PL is already programmed

  #205 opened a year ago by joelievt
  2

• Interpolation between pulses in AxisSgInt4V1

  #202 opened a year ago by sebastianhorvath
  2

• A question regarding reset value of fifo_empty_r in axi_mst_write.sv

  #197 opened a year ago by Ri-chard-Wu
  2

• Hardware loop frequency sweep ZCU216

  #194 opened a year ago by Jalbanese02
  1

• timming-violation for both zcu111 and zcu216 in 87895db

  #190 opened a year ago by CCvitaminHsieh
  4

• the link to gerber files is broken in qick/hardware/README.md

  #177 opened a year ago by ikd-sci
  2

• Using ZCU216 for controlling multiple flux qubits

  #163 opened a year ago by JavierSerranoGarcia
  6

• Variable phase in ZCU216

  #164 opened a year ago by rodolfocarobene
  1

• ADC reading reading is too small

  #170 opened a year ago by TinaHsing
  1

• Determine Whether to Play Pulse or Not Based on Readout Results

  #145 opened a year ago by TinaHsing
  3

• Resetting ADC phase

  #168 opened a year ago by tristanlorriaux
  3

• Can DAC228_T0_CH3 be used?

  #167 opened a year ago by zhizhenzhong
  2

• Unwanted triggering low voltage plateau

  #159 opened a year ago by tristanlorriaux
  3

• Possible mismatch in time registers name

  #155 opened a year ago by rodolfocarobene
  4

• Adding more DACs and ADCs (full capacity of the ZCU216) ?

  #156 opened a year ago by tristanlorriaux
  2

• Fast reset and hardware classification

  #154 opened a year ago by rodolfocarobene
  4

• Module import gives extraneous warning when used on non-Zynq platform

  #157 opened a year ago by ionick
  1

• Duration Sweepers

  #149 opened 2 years ago by rodolfocarobene
  2

• Behaviour not expected in the reconstruction of signals by the DACs on a ZCU111

  #143 opened 2 years ago by JavierSerranoGarcia
  4

• Gain: DAC units mapping to dbm

  #144 opened 2 years ago by EeshGupta
  2

• Maximum number of pulses

  #142 opened 2 years ago by rodolfocarobene
  4

• ZCU216 DAC seems to not follow the external ref 10MHz clock.

  #139 opened 2 years ago by tristanlorriaux
  5

• Multiplexed readout phase

  #140 opened 2 years ago by rodolfocarobene
  4

• Dynamic range control for ADC

  #141 opened 2 years ago by mutasemodeh
  1