osherg10

osherg10's Stars

• skiwee45/Airplane_Tutorial

  Language:C#4421

• SystemErrorWang/White-box-Cartoonization

  Official tensorflow implementation for CVPR2020 paper “Learning to Cartoonize Using White-box Cartoon Representations”

  Language:Python4k737

• znxlwm/pytorch-CartoonGAN

  Pytorch implementation of CartoonGAN (CVPR 2018)

  Language:Python38673

• jyoti0225/Photo-Sketching

  Converts image to a digital pencil sketch using OpenCV and Python

  Language:Jupyter Notebook43

• BKHMSI/Sketchback

  Keras implementation of sketch inversion using deep convolution neural networks (synthesising photo-realistic images from pencil sketches)

  Language:Jupyter Notebook5724

• jjxxmiin/PhotoSketch_Pytorch

  PhotoSketch

  Language:Jupyter Notebook6

• ArduPilot/ardupilot

  ArduPlane, ArduCopter, ArduRover, ArduSub source

  Language:C++11.1k17.6k

• skordal/potato

  A simple RISC-V processor for use in FPGA designs.

  Language:VHDL26344

• simonace/nand2tetris_vhdl

  Language:VHDL5

• wuhanstudio/nand2tetris-iverilog

  A 16-bit Hack CPU from scratch on FPGA.

  Language:Verilog4511

• jcoglan/nand2tetris

  Solutions for http://www.nand2tetris.org/

  Language:Assembly8545

• robseb/Django2FPGAdemo

  Demonstration how to build a Management Web interface to interact with the FPGA fabric and change the FPGA configuration with the Django Framework

  Language:Python114

• willzma/Conte-Lake

  A 32-bit RISC processor built in Verilog for CS 3220 Spring 2017

  Language:Verilog41

• robseb/rsyocto

  🤖 SoCFPGA: Open-Source Embedded Linux Distribution with a highly flexible build system, developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

  Language:Python10326