This project contains synthesized verilog codes for Encryption/Decryption of secure IP stream using Advanced Encryption Standard (AES) algorithm and implemented through Field Programmable Gate Array (FPGA). This is a optimized code for handling IP packets and encrypt/decrypt the data part using a 128-bit block cipher.
osok/IP_Stream_Encryption_using_AES_and_FPGA
This project contains synthesized verilog codes for Encryption/Decryption of secure IP stream using Advanced Encryption Standard (AES) algorithm and implemented through Field Programmable Gate Array (FPGA). This is a very optimized code for handling IP packets and encrypt/decrypt the data part using a 128-bit block cipher. It uses a pipeline and sub pipeline architecture.
Verilog