XiangShan (香山) is an open-source high-performance RISC-V processor project.
Detailed documents will be released in the near future.
Copyright 2020-2021 by Institute of Computing Technology, Chinese Academy of Sciences.
A tutorial on XiangShan is held at RISC-V World Conference China 2021 in June. Multiple technical reports will be included in the conference as well. Stay tuned!
For more information, please refer to this link.
The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on this branch, which has been developed since June, 2020. The current version of XiangShan, also known as Nanhu (南湖), is still under development on master branch.
The micro-architecture overview is shown below.
Some of the key directories are shown below.
.
├── fpga # supported FPGA boards and files to build a Vivado project
├── read-to-run # pre-built simulation images
├── scripts # scripts for agile development
└── src
├── test # test files (including diff-test, module-test, etc.)
└── main/scala # design files
├── bus/tilelink # tilelink utils
├── device # virtual device for simulation
├── difftest # diff-test chisel interface
├── system # SoC wrapper
├── top # top module
├── utils # utilization code
├── xiangshan # main design code
└── xstransforms # some useful firrtl transforms
- Run
make verilog
to generate verilog code. The output file isbuild/XSTop.v
. - Refer to
Makefile
for more information.
- Set environment variable
NEMU_HOME
to the absolute path of the NEMU project. - Set environment variable
NOOP_HOME
to the absolute path of the XiangShan project. - Set environment variable
AM_HOME
to the absolute path of the AM project. - Install
mill
. Refer to the Manual section in this guide. - Clone this project and run
make init
to initialize submodules.
- Install Verilator, the open-source Verilog simulator.
- Run
make emu
to build the C++ simulator./build/emu
with Verilator. - Refer to
./build/emu --help
for run-time arguments of the simulator. - Refer to
Makefile
andverilator.mk
for more information.
Example:
make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j10
./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so
In the development of XiangShan, some sub-modules from open source community are employed. All relavant usage is listed below.
Sub-module | Source | Detail |
---|---|---|
L2 Cache/LLC | Sifive block-inclusivecache | We enhance the function and the timing of the original module, finally turning it into a Cache generator that can be configured as L2/LLC. |
Diplomacy/TileLink | Rocket-chip | We reused the diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. |
FPU | Berkeley hardfloat | We use Berkeley-hardfloat as our FPU and implement a SRT-4 div/sqrt unit for it. Additionally, we split the FMA pipeline to optimize the timing. |
We are grateful for the support of the open source community and encourage other open source projects to reuse our code within the scope of the license.