Designed an asynchronous FIFO of depth 2^n and relevent pointer synchronizing circuits in Verilog and verified its functionality.
References
The design is greatly inspired from : http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
I found this blog also very helpful: https://zipcpu.com/blog/2018/07/06/afifo.html
Implemented SPI master which supports all 4 modes of SPI and verified functionality using Verilog.
References
Motorola SPI Specs : http://www.ee.nmt.edu/~rison/datasheets/ee308/S12SPIV2.pdf
Designed and implemented in Verilog to add Built in Self Test (BIST) capabilities to a given combinational logic. The Test Pattern Generator (TPG), Output Response Analyzer (ORA) and BIST controller were designed. A 1-bit full adder was considered as the circuit under test (CUT) with faults injected at various nets to verify the functionality.