/kicadtoverilog

Export from Hierachical KiCad 6 schematic to Verilog

Primary LanguagePython

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KiCad to Verilog

Hierarchical Verilog Export for Kicad 6
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Table of Contents
  1. About The Project
  2. Getting Started
  3. Usage
  4. Roadmap
  5. Contributing
  6. License
  7. Contact
  8. Acknowledgments

About The Project

Product Name Screen Shot

Python3 script and KiCad symbol library, to support export of structural, synthesizable Verilog from KiCad schematic sheets. This script understands the hierarchy of KiCad sheets. Each sheet is supported as a Verilog Module.

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Built With

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Getting Started

TBD

Prerequisites

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Usage

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Roadmap

  • [] Feature 1
  • [] Feature 2
  • [] Feature 3
    • [] Nested Feature

See the open issues for a full list of proposed features (and known issues).

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Contributing

Contributions are what make the open source community such an amazing place to learn, inspire, and create. Any contributions you make are greatly appreciated.

If you have a suggestion that would make this better, please fork the repo and create a pull request. You can also simply open an issue with the tag "enhancement". Don't forget to give the project a star! Thanks again!

  1. Fork the Project
  2. Create your Feature Branch (git checkout -b feature/AmazingFeature)
  3. Commit your Changes (git commit -m 'Add some AmazingFeature')
  4. Push to the Branch (git push origin feature/AmazingFeature)
  5. Open a Pull Request

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License

Distributed under the MIT License. See LICENSE.txt for more information.

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Contact

Project Link: https://github.com/palazzol/kicadtoverilog

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Acknowledgments

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