/MS-Labs

Primary LanguageVHDL

Microelectronic Systems Laboratories

Languages developement

Index

Team

Labs

Lab1

VHDL and Synthesis

  • generic Multiplexer
  • generic Ripple Carry Adder
  • Accumulator
  • basic ALU

Lab2

Hierarchical Arithmetical Blocks

  • Pentium 4 Adder
    • Sparse Tree Carry Generator
    • Carry Select-like Sum Generator
  • Parallel Multiplier based on Booth's algorithm

Lab3

Windowed Register File and Low-Power Synthesis

  • Register File
  • Windowed Register File (Register File + Register Management Logic)
  • SI-PI-SO-ALU for Low-Power Synthesis

Lab4

Control Unit for a simplified version of the DLX datapath:

  • Hardwired CU
  • FSM CU
  • Microprogrammed CU

Lab5

Switch level analysis with ELDO:

  • Gate characterization for output load
  • Gate characterization for transition time
  • Comparison between gates of different size
  • Comparison between high speed and low leakage optimization
  • FF

Lab6

Physical Design using Innovus:

  • RCA (128 bit)
  • P4 adder (32 bit)
  • Booth's Multiplier