The aim is to create an environment for fpga development for Parallella using Yocto. Longer term this will move to use open hardware libaries to build the parallella fpga
START IN peteasa/parallella for a full description of the project
- Xilinx Vivado 2015.4.
Note each of these sources is likely to be covered by a different license. Please refer to the original source for copyright information
Tutorials - Tutorial index for the peteasa/parallella project
- OH! - Open Hardware for Chip Designers
- Analog Devices Inc HDL IP - Analog Devices HDL libraries and projects used in this project
- Xilinx device tree scripts - used to create the device tree template from the FPGA design