Increase elink data rate (FPGA-->epiphany)

[aolofsson]

Currently the elink frequency is not running at full speed. After we have the Vivado project released, the next step will be to push the elink transmit frequency to 500Mz (ie 1GB/s downstream bandwidth to the Epiphany).

Tasks needed:
-instantiate a DMA master engine on the PL to pull data from DRAM and deposit on the elink
-create driver layer to enable using the dma with p_read/p_write
-optimize axi interfaces to work for 1GB/s throughput
-push the tx_lclk/lvds_serdes frequency to 500MHz (synthesis+place and route not trivial...)