Pinned Repositories
DAJABA
Failed
fpga-ml-accelerator
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
spi_test
nofile
SyncFIFO
Systemverilog
test
Test Repository
Verification-of-FIFO-using-SystemVerilog
Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog. Created components like generator, driver, monitor, scoreboard, interface, environment, and testbench.
parkjonguk's Repositories
parkjonguk/DAJABA
parkjonguk/Failed
parkjonguk/fpga-ml-accelerator
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
parkjonguk/spi_test
nofile
parkjonguk/SyncFIFO
parkjonguk/Systemverilog
parkjonguk/test
Test Repository
parkjonguk/Verification-of-FIFO-using-SystemVerilog
Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog. Created components like generator, driver, monitor, scoreboard, interface, environment, and testbench.