Generic Verilog project template for use with OSS digital design tools
This project is dependent on the oss-cad-suite by YosysHQ.
Press the Use this template button on the Github page of this repository.
This project has the given folder structure. Some features include:
├── modules
│ └── pipe
├── README.md
└── src
├── rtl
└── sim
└── makefile
See the open issues for a list of proposed features (and known issues).
- Top Feature Requests (Add your votes using the 👍 reaction)
- Top Bugs (Add your votes using the 👍 reaction)
- Newest Bugs
Reach out to the maintainer at one of the following places:
- GitHub issues
- Contact options listed on this GitHub profile
The original setup of this repository is by Patric A.B.
For a full list of all authors and contributors, see the contributors page.
This project is licensed under the MIT license.
See LICENSE for more information.