paulscherrerinstitute/vivadoIP_power_sink
Toggle FFs, SRLs and BRAMs to drain power for testing purposes
VHDLNOASSERTION
Issues
- 1
- 0
DSPs per column, architecture differences
#4 opened by dduerner - 1
BSP driver Makefile issue in Vitis 2020.1
#2 opened by dduerner - 0
Synth fails on lowest settings
#1 opened by dduerner