pawks

avst_adder

Example setup for UVM driven Icarus Verilog Simulation

avst_adder_vl

Reference eUVM testbench for verilator

pawks.github.io

riscv-arch-test

riscof

riscv-config

RISC-V Configuration Validator

riscv-ctg

riscv-isac

pawks/pawks.github.io

pawks/avst_adder

Example setup for UVM driven Icarus Verilog Simulation

pawks/avst_adder_vl

Reference eUVM testbench for verilator

pawks/bsc

Bluespec Compiler (BSC)

pawks/COLAB

pawks/custom-mods

pawks/fp-test-stats

pawks/gem5

The official repository for the gem5 computer-system architecture simulator.

pawks/learn4haskell

👩‍🏫 👨‍🏫 Learn Haskell basics in 4 pull requests

pawks/lfx-mentorship

pawks/mbedtls

An open source, portable, easy to use, readable and flexible SSL library

pawks/pandoc-latex-template

A pandoc LaTeX template to convert markdown files to PDF or LaTeX.

pawks/polybar-pulseaudio-control

A feature-full Polybar module to control PulseAudio

pawks/riscof

pawks/riscv-arch-test

pawks/riscv-binutils-gdb

RISC-V backports for binutils-gdb. Development is done upstream at the FSF.

pawks/riscv-ctg

pawks/riscv-isa-sim

Spike, a RISC-V ISA Simulator

pawks/riscv-isac

pawks/river_core

RiVer Core is an open source Python based RISC-V Core Verification framework.

pawks/SAP