AVR (ATMEGA328p) Verilog model with UART Simulation model and toolchain using verilator, icarus and gtkwave SKEL CPU MODEL CORE IO TIMER/COUNTER INTERRUPT UART SIMULATION MODELS Icarus TestBench (Verilog) Verilator TestBench (Verilog) Verilator Interface (C++) SOFTWARE FRAMEWORK C/C++ ASM HELPER TOOLS Makefiles