pearson78

ankur_ldpc

can

CAN Protocol Controller

CAN-Bus-Controller

An CAN bus Controller implemented in Verilog

Design-and-Verification-of-LDPC-Decoder

- Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab.

dvb_s2_ldpc_decoder

DVB-S2 LDPC Decoder

e200_opensource

The Ultra-Low Power RISC Core

gr-ldpc

hw

RTL, Cmodel, and testbench for NVDLA

LDPC

C and MATLAB implementation for LDPC encoding and decoding

LDPC-1

pearson78/ankur_ldpc

pearson78/can

CAN Protocol Controller

pearson78/CAN-Bus-Controller

An CAN bus Controller implemented in Verilog

pearson78/Design-and-Verification-of-LDPC-Decoder

- Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab.

pearson78/dvb_s2_ldpc_decoder

DVB-S2 LDPC Decoder

pearson78/e200_opensource

The Ultra-Low Power RISC Core

pearson78/gr-ldpc

pearson78/hw

RTL, Cmodel, and testbench for NVDLA

pearson78/LDPC

C and MATLAB implementation for LDPC encoding and decoding

pearson78/LDPC-1

pearson78/LDPC-codes

Software for Low Density Parity Check codes

pearson78/LDPC_Dec

pearson78/LDPC_Decoder

Low Density Parity Check Decoder

pearson78/riscv-linux

RISC-V Linux Port

pearson78/verilog_cordic_core

configurable cordic core in verilog

pearson78/zero-riscy