pedrocgr
Computer Engineering Student @ UFPE in Brazil | Member @ RoboCin Autonomous Drone Crew
Federal University Of PernambucoRecife, Brazil
Pinned Repositories
deep-learning-competition
Competition entries, deep learning and machine learning solutions
ess
ess_assignment
groove-app
The ESS Base Project is a repository designed to kickstart new projects for the Software Engineering and Systems discipline at CIn-UFPE. It aims to simplify the project initiation process providing a solid base by offering an initial structure, architecture, configurations, and implementation examples.
ihs-game
Infracom
UDP Socket server/client program in python
Infraestrutura_Hardware
Resumos para a cadeira de Infraestrutura de Hardware
pedrocgr.github.io
pulp-projectic
Implementing the CV32E40P Core from PULP Platform
python-classifier
Statistics class group project, exploratory data analysis and machine learning
robocinDrone
Autonomous drone that follows a line
pedrocgr's Repositories
pedrocgr/Infraestrutura_Hardware
Resumos para a cadeira de Infraestrutura de Hardware
pedrocgr/deep-learning-competition
Competition entries, deep learning and machine learning solutions
pedrocgr/ess
ess_assignment
pedrocgr/groove-app
The ESS Base Project is a repository designed to kickstart new projects for the Software Engineering and Systems discipline at CIn-UFPE. It aims to simplify the project initiation process providing a solid base by offering an initial structure, architecture, configurations, and implementation examples.
pedrocgr/ihs-game
pedrocgr/Infracom
UDP Socket server/client program in python
pedrocgr/pedrocgr.github.io
pedrocgr/pulp-projectic
Implementing the CV32E40P Core from PULP Platform
pedrocgr/python-classifier
Statistics class group project, exploratory data analysis and machine learning
pedrocgr/robocinDrone
Autonomous drone that follows a line
pedrocgr/Infracom-main
pedrocgr/PianoChordDetection
Detection of Piano Major and Minor Triads(Chords) Using Deep Learning and Feature Extraction: FFT, Chroma Features, MFCCS
pedrocgr/RISC-V-PipeLine_test
SystemVerilog realization of RISC-V processor