pgate1/NES_on_FPGA

implemented NES on an FPGA.

NES on FPGA

Implemented NES on an FPGA.
The hardware discription language is original expanded SFL+.
(SFL: Structured Function description Language Tutorial)

FPGA data is available at:
https://pgate1.at-ninja.jp/NES_on_FPGA/index.html#release