philippdiethelm

philippdiethelm's Stars

• darklife/darkriscv

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  Language:Verilog2.1k289

• datenlord/open-rdma

  RoCE v2 hardware and software implementation

  13229

• microsoft/NetworkDirect

  NetworkDirect Service Provider Interface

  Language:C++6130

• Gabriele-bot/100G-verilog-RoCEv2-lite

  TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.

  Language:Verilog4

• datenlord/blue-udp

  The hardware implementation of UDP in Bluespec SystemVerilog

  Language:Bluespec74

• sach/System-Verilog-Packet-Library

  System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers

  Language:SystemVerilog7223

• w180112/RDMA-example

  RDMA programming example

  Language:C158

• RHSResearchLLC/PicoEVB

  Public repository for PicoEVB (Xilinx Artix XC7A50T based)

  Language:C24865

• crystalsnetworkdev/NanoEVB

  Language:VHDL2

• alexforencich/verilog-axis

  Verilog AXI stream components for FPGA implementation

  Language:Python750229

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.4k708

• microsoft/xdp-for-windows

  XDP speeds up networking on Windows

  Language:C37842

• rigtorp/SPSCQueue

  A bounded single-producer single-consumer wait-free and lock-free queue written in C++11

  Language:C++930130

• rigtorp/awesome-lockfree

  A collection of resources on wait-free and lock-free programming

  1.8k171

• rigtorp/MPMCQueue

  A bounded multi-producer multi-consumer concurrent queue written in C++11

  Language:C++1.2k169

• mcjtag/eth_switch

  Verilog Ethernet Switch (layer 2)

  Language:Verilog3711