Pinned Repositories
automatic-verilog
automatic-verilog based on vimscript
basic_verilog
Must-have verilog systemverilog modules
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
constellation
A Chisel RTL generator for network-on-chip interconnects
Cores-SweRV
SweRV EH1 core
corundum
Open source FPGA-based NIC and platform for in-network compute
gen_amba_2021
AMBA bus generator including AXI4, AXI3, AHB, and APB
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
net
opentitan
OpenTitan: Open source silicon root of trust
phoenixfegn's Repositories
phoenixfegn/poly1305
Hardware implementation of the poly1305 message authentication function.
phoenixfegn/automatic-verilog
automatic-verilog based on vimscript
phoenixfegn/basic_verilog
Must-have verilog systemverilog modules
phoenixfegn/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
phoenixfegn/constellation
A Chisel RTL generator for network-on-chip interconnects
phoenixfegn/Cores-SweRV
SweRV EH1 core
phoenixfegn/corundum
Open source FPGA-based NIC and platform for in-network compute
phoenixfegn/gen_amba_2021
AMBA bus generator including AXI4, AXI3, AHB, and APB
phoenixfegn/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
phoenixfegn/opentitan
OpenTitan: Open source silicon root of trust
phoenixfegn/aes
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
phoenixfegn/chacha
Verilog 2001 implementation of the ChaCha stream cipher.
phoenixfegn/corsair
Control and Status Register map generator for HDL projects
phoenixfegn/Coursera-ML-AndrewNg-Notes
吴恩达老师的机器学习课程个人笔记
phoenixfegn/deeplearning_ai_books
deeplearning.ai（吴恩达老师的深度学习课程笔记及资源）
phoenixfegn/firesim
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
phoenixfegn/ituring_books
图灵程序设计丛书分享
phoenixfegn/muriscv-nn
muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.
phoenixfegn/oh_verilog
Verilog library for ASIC and FPGA designers
phoenixfegn/PeakRDL
Control and status register code generator toolchain
phoenixfegn/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
phoenixfegn/Practical-Cryptography-for-Developers-Book
Practical Cryptography for Developers: Hashes, MAC, Key Derivation, DHKE, Symmetric and Asymmetric Ciphers, Public Key Cryptosystems, RSA, Elliptic Curves, ECC, secp256k1, ECDH, ECIES, Digital Signatures, ECDSA, EdDSA
phoenixfegn/pupl_axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
phoenixfegn/pymtl3
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
phoenixfegn/riscv-isa-manual
RISC-V Instruction Set Manual
phoenixfegn/rocket-chip
Rocket Chip Generator
phoenixfegn/sifive-blocks
Common RTL blocks used in SiFive's projects
phoenixfegn/usb3_pipe
USB3 PIPE interface for Xilinx 7-Series
phoenixfegn/verilog-axi
Verilog AXI components for FPGA implementation
phoenixfegn/verilog-ethernet
Verilog Ethernet components for FPGA implementation