Pinned Repositories
abc
ABC: System for Sequential Logic Synthesis and Formal Verification
cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
common_cells
DEVELOPMENT FORK
croc-osic-tools
Open-source EDA tools used for pulp croc-soc.
cva6
Personal fork of the PULP-fork of CVA6.
mockturtle-dev
C++ logic network library (development fork)
osic-tools-dev
IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
register_interface
Generic Register Interface (contains various adapters)
riscv-isa-sim
Spike, a RISC-V ISA Simulator with Xpulp ISA extension
yug-presentation
Yosys User Group #5 - Examples & Presentation
phsauter's Repositories
phsauter/croc-osic-tools
Open-source EDA tools used for pulp croc-soc.
phsauter/yug-presentation
Yosys User Group #5 - Examples & Presentation
phsauter/abc
ABC: System for Sequential Logic Synthesis and Formal Verification
phsauter/cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
phsauter/common_cells
DEVELOPMENT FORK
phsauter/cva6
Personal fork of the PULP-fork of CVA6.
phsauter/mockturtle-dev
C++ logic network library (development fork)
phsauter/osic-tools-dev
IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
phsauter/register_interface
Generic Register Interface (contains various adapters)
phsauter/riscv-isa-sim
Spike, a RISC-V ISA Simulator with Xpulp ISA extension
phsauter/riscv-opcodes
RISC-V Opcodes with Xpulp ISA extension
phsauter/riscv-tests
Development of a complete set of functional tests for the Xpulp ISA extension
phsauter/svase
Development and experimentation
phsauter/yosys
Yosys Open SYnthesis Suite
phsauter/TO_May2024_basilisk