physical-computation/Sail-RV32I-common

Issues

• Possible timing issue

  #10 opened 5 years ago by rjlv2
  1

• Check branch predictor state machine

  #19 opened 5 years ago by rjlv2
  1

• Look into simplifying data memory

  #27 opened 6 years ago by rjlv2
  0

• Further work on CSR

  #6 opened 6 years ago by rjlv2
  1

• Possible hazard in combinational logic of control unit

  #25 opened 6 years ago by rjlv2
  1

• JALR might not be compliant with specifications.

  #26 opened 6 years ago by rjlv2
  0

• Implement CSR

  #18 opened 6 years ago by rjlv2
  2

• Forwarding Unit might not actually require ternary operators.

  #24 opened 6 years ago by rjlv2
  0

• Look into bottleneck in memory access

  #17 opened 6 years ago by rjlv2
  1

• Modified data memory

  #21 opened 6 years ago by btsouts
  0

• Implement a modified Harvard architecture, with separate instruction and data caches but single memory.

  #15 opened 6 years ago by rjlv2
  1

• Instruction memory uses LC

  #13 opened 6 years ago by harrysarson
  1

• Differentiate CSRR instructions from ECALL/EBREAK

  #16 opened 6 years ago by rjlv2
  0

• Code cleanup to meet coding conventions

  #12 opened 6 years ago by phillipstanleymarbell
  3

• LICENCE

  #5 opened 6 years ago by harrysarson
  1

• Merge RV32_I and narvie's cpu.v

  #2 opened 6 years ago by harrysarson
  0

• CSR forwarding bug

  #8 opened 6 years ago by rjlv2
  1