CompArch Lab 0: Full Adder on FPGA

Due: September 27

This lab assignment will develop one of the basic building blocks for your processor and introduce you to FPGAs.

You should complete HW2 before beginning this lab. Lab 0 depends on building blocks created in HW2.

You will work in groups of 2-3. If you have not yet formed a group, do so on the team formation spreadsheet (link is on Piazza).

Setup

Install the required software by following the instructions on the course website. If you followed the virtual machine instructions, you should already have everything you need.

Check out an FPGA kit for your team.

Verify FPGA Tool Chain

This portion of the exercise is not collected. It is intended only to verify that your full tool chain is correctly configured, and will save you headache later.

The easiest way to accomplish this is to attend the FPGA tutorial: Wednesday 9/20 at 8pm in the library.

Ensure that the switches, buttons, and LEDs on your FPGA board are functional. You may want to try instantiating various gates for additional practice.

4 bit Full Adder - simulation

In HW2 you constructed several modules in structural Verilog and then tested them with the iverilog simulator. Re-use the Full Adder component to create a 4 bit Full Adder.

This module must be in adder.v, and must have the following definition:

module FullAdder4bit
(
  output[3:0] sum,  // 2's complement sum of a and b
  output carryout,  // Carry out of the summation of a and b
  output overflow,  // True if the calculation resulted in an overflow
  input[3:0] a,     // First operand in 2's complement format
  input[3:0] b      // Second operand in 2's complement format
);
    // Your Code Here
endmodule

Your code will be verified by our own test bench, so it is critical your module definition and name matches.

Within this module, you will need to instantiate four of your single bit full adders and then appropriately wire them. Reference a single bit of a bus with the bracket operator: the first (least significant) bit of a is a[0].

Each of the gates within your design should have a delay of 50 units of time.

Test Bench - simulation

Create a test bench that exercises your 4 bit full adder, and verifies proper operation of its three outputs (Sum, Carry Out, Overflow). It is probably in your best interest to write this at the same time you write the module that it tests.

An exhaustive test requires 2⁽⁴⁺⁴⁾= 256 test cases. Select a subset of those test cases that provides an appropriate level of coverage. It may be helpful for you to explicitly document what each subset of test cases are testing. For example, select several test cases that test the overflow flag and preface them with $display(“Test Overflow:”);.

When a test case fails, a well-designed tester should make it easy to identify possible locations of the cause.

Each time that your test bench catches an error in your design, document it in your write-up. Include the test case, the cause of the error, and the fix that made the test case pass.

Note that your test bench will need to account for the gate delays in your design. After setting the inputs, be sure to wait sufficiently long for the result to stabilize.

Your test harness must be in adder.t.v, and must instantiate FullAdder4bit from adder.v (again, for our test bench tester).

Full Adder on FPGA

Use your adder.v and the provided lab0_wrapper.v to create a Vivado project, and load your tested 4-bit full adder design onto the FPGA board.

Challenge: Write your own interface to the Zybo board that lets you completely test your 4-bit full adder without using lab0_wrapper.v.

Verify correct operation by manually inputting test cases with the switches and buttons and examining the results on the LEDs. Choose 16 test cases that provide a reasonable amount of coverage – you’ve already tested the design in ModelSim, so you do not need to provide the same level of coverage again.

Provide photos or a gif of your FPGA correctly computing one of the 16 test cases you chose.

In your report include the full 16 test cases, why you chose them and their results.

Report

Create a semi-formal lab report. Minimally, it should include the following:

Waveforms showing the full adder stabilizing after changing inputs. What is the worst case delay?
An explanation of your test case strategy. Why did you choose the tests you did?
A list of test case failures and the changes to your design they inspired.
A summary of testing performed on the FPGA board.
Summary statistics of your synthesized design from Vivado (Propagation Delay, Resources Used, etc)

You may optionally include additional information, such as the timing performance or design tradeoffs of your modules.

The report should be a single PDF or MarkDown file.

Submission

Push your files to your team GitHub repository. It should include the following:

Your report, as a PDF or MarkDown file
Verilog code for
1. 1 bit full adder
2. 4 bit full adder
3. 4 bit full adder test bench
4. The top level module for synthesis onto the FPGA
Associated run scripts, e.g. Makefile

Submit a pull request to the course repo (CompArchFA17/Lab0) for us to respond to with feedback.

Hints

Now that we have signals that are more than 1 bit wide, it makes sense to refer to them using buses. This allows us to reference all of the related bits in a convenient manner.

If iverilog gives really cryptic errors about missing declarations that aren’t actually missing, look at the module above to see if you missed an end.

Rubric

Adder Functionality	25
Sum	15
Carry Out, Overflow	5
Gate Delays	5


Test Bench	15
Verifies Sum	5
Verifies Carryout	5
Verifies Overflow	5


FPGA (Verified in report)	20
Tutorial / Verify tool chain	0
16 test cases are well chosen	10
Pass 16 test cases	5
Summary statistics	5

Report	35
Timing waveforms explained	5
Test bench explanation	20
Test bench failures / resulting changes	10


Code commented (Nice but not excessive)	5

poosomooso/Lab0