Port error in generated instantiation template
zzkiob opened this issue · 4 comments
When I give an initial value to an output reg port, then the generated instantiation template has a error port. The code below will show the issue. Code 1 shows the source code and Code 2 shows the generated instantiation template,surely the d0 port in instantiation template is a wrong port.
Code 1:
module t1(
input clk,
input rst,
output reg [31:0] dout = 32'd0);
always @(posedge clk or posedge rst) begin
if (rst) begin
dout <= 32'd0;// reset
end
else begin
dout <= dout + 1'b1;
end
end
endmodule
Code 2:
t1 inst_t1 (.clk(clk), .rst(rst), .d0(d0));
Yeah, I didn't make to parse port with initial value. It is not synthesizable, isnt' it ?
I don't know whether it is synthesizable for ASIC, but it is synthesizable for FPGA. FPGA supports initial value for registers.
OK, I'll try it. Thanks.