poucotm/Verilog-Gadget

Instantiate module question about sv unpacked array port

AshLeung opened this issue · 2 comments

AshLeung commented

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Hi, as the picture shows, if I instaniate a module with unpacked array port, it will parse the port name incorrectly. plz fix this bug.

poucotm commented

@AshLeung , VG package is mainly for verilog not systemverilog. To support systemverilog for all functions including generating testbench, it will take a long time. But I've patched simply for instantiation. Could you try v1.12.1 ?

AshLeung commented

Thank you! It works.