/eda-collection

EDA-Collection

This is a collection of electronic design automation surveys, courses, and open source tools.

Table of contents

  • [Books and Surveys]
  • [Courses and Tutorials]
  • [Workshops on Open Source EDA]
  • [Open Source Tools (code available)]
  • [Open Access Tools (binary only)]

Books and Surveys

Overview

Synthesis

Placement

Routing

Courses and Tutorials

Workshops on Open Source EDA

Open Source Tools (code available)

ASIC Flow

  • qflow (Dr. R. Timothy Edwards), GNU General Public License
    • A Digital Flow using Open Source EDA Tools.
  • VSDFLOW (VLSI System Design), "available for download for FREE"
    • An automated RTL-to-GDS flow for programmers, hobbyists, and small-scale entrepreneurs.
  • OpenRoad (UCSD), various licenses (BSD 2-Clause, BSD 3-Clause, GPL 3.0, ISC, etc.)
    • Aim to develop open-source tools that achieve autonomous, 24-hour layout implementation.
  • Ophidian (UFSC)
    • An open-source library for physical design research and teaching.
  • Rsyn (FURG)
    • An Extensible Physical Synthesis Framework.
  • gEDA
    • Working on a full GPL'd suite and toolkit of Electronic Design Automation tools.

FPGA Flow

  • VTR (Toronto)
    • An CAD flow tool for FPGA including ODIN-II, ABC, VPR place, and VPR route.
  • RapidWright (Xilinx)
    • Provide Vivado Interface for users to build customized FPGA implementations.
    • Similar projects: Torc, RapidSmith, and RapidSmith2
  • IceStorm (Clifford Wolf)
    • Aims at reverse engineering and documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.
    • A working fully open source flow with Yosys and Arachne-pnr.
  • FPGA CAD Framework (Ghent Univ.)
    • A Java framework focused on rapid prototyping of new CAD algorithms for FPGA compilation.
  • Rebit
    • A low level configuration analysis and for the debugging and validation of the bitstream files of architectures that exploit dynamic partial reconfiguration on Xilinx FPGAs.
  • Sdaccel-chisel-integration
    • A wrapper in Chisel for using RTL kernels into SDAccel 2017.1.
  • hCODE (Kumamoto Univ.)
    • A tool to simplify the creation, sharing, and software integration of FPGA hardware accelerators.
  • Automata to Routing (U.Va.)
    • An open-source toolchain to design and evaluate island style spatial automata processing architectures.
  • DATuner (Cornell, PKU)
    • A parallel bandit-based approach for autotuning FPGA compilation.

High-level Synthesis

  • LegUp (Toronto)
    • A high-level synthesis tool to improve C to Verilog synthesis without building an infrastructure from scratch.
  • GAUT (Université Bretagne Sud)
    • A high-level synthesis tool from algorithm to hardware architecture.
  • PandA (Politecnico di Milano)
    • A usable framework that will enable the research of new ideas in the HW-SW Co-Design field.
  • FCUDA (ADSC High Level Synthesis Team)
    • A source-to-source transformation framework that takes CUDA kernels with FCUDA annotation pragmas as input and produces a synthesizable C code.

DSL and IR

  • HeteroCL (Cornell, UCLA)
    • A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing.
  • Chisel (Berkeley)
    • A hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.
  • FIRRTL (Berkeley)
    • An intermediate representation (IR) for digital circuits designed as a platform for writing circuit-level transformations.
  • BAG: Berkeley Analog Generator (Berkeley)
    • A Python-based circuit design platform that aims to automate analog circuit design, but at the same time give the user full visibility and control over every step in the design flow.

Logic Synthesis

  • ABC (Berkeley)
    • A sequential logic synthesis and formal verification tool.
  • LLDHL
    • A logic synthesis and manipulation infrastructure for FPGAs.
  • Yosys (Clifford Wolf)
    • A framework for Verilog RTL synthesis, used by qflow and OpenROAD

Placement

  • DREAMPlace (UT Austin)
    • A GPU-accelerated analytical placement tool.
  • OpenROAD RePlAce (UCSD)
    • A global placement tool with advancing solution quality and routability validation.
  • RippleFPGA (CUHK)
    • A simultaneous pack-and-place algorithm for FPGA.
  • arachne-pnr
    • A place and route tool for FPGAs.
  • nextpnr
    • A vendor neutral, timing driven, FOSS FPGA place and route tool.
  • qflow Graywolf
    • A placement tool in VLSI design and used together with qflow.

Routing

  • qflow Qrouter
    • A detailed router based on the standard Lee maze router algorithm.
  • Dr. CU (CUHK)
    • VLSI detailed routing tool.
  • FGR (UMich)
    • A global router based on Lagrange Multipliers and won the 1st place in ISPD 2007 contest.
  • BoxRouter (UT Austin)
    • A global router for ultimate routability and won the 2nd place in ISPD 2007 contest.
  • NTHU-Route (NTHU)
    • A fast and stable global router and won the 1st place in ISPD 2008 contest.
  • FastRoute (Iowa State)
    • A global routing tool for VLSI back-end design.
  • FLUTE (Iowa State)
    • A very fast and accurate technique for rectilinear Steiner minimal tree (RSMT) construction.
  • SALT (CUHK)
    • A tool for generating VLSI routing topology.

Logic Simulation

  • Verilator
    • A fast free Verilog/SystemVerilog simulator.
  • GHDL
    • An open-source simulator for the VHDL language.
  • FreeHDL
    • A free, open source, GPL'ed VHDL simulator for Linux.
  • TkGate
    • A digital circuit editor and simulator with a Tcl/Tk-based interface.

Timing Analysis

  • OpenTimer (UIUC)
    • A High-Performance Timing Analysis Tool for VLSI Systems.
  • OpenROAD OpenSTA
    • A gate level static timing verifier.

Circuit Analysis

  • ngspice
    • Open source spice simulator.
  • SPICE (Berkeley)
    • A general-purpose circuit simulation program for nonlinear dc, nonlinear transient, and linear ac analyses.
  • mixedsim (Isotel)
    • Mixed signal simulation with Verilog.
  • Gnucap: GNU Circuit Analysis Package
    • A modern "post-spice" analog and mixed signal circuit simulator.
  • Qucs: Quite Universal Circuit Simulator
    • Setup a circuit with a graphical user interface (GUI) and simulate the large-signal, small-signal and noise behaviour of the circuit.
  • Xyce (Sandia NL)
    • An open source, SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms.

Physical Analysis

  • FreeCAD
    • An open-source parametric 3D modeler made primarily to design real-life objects of any size.
  • Fast Field Solvers (FastFieldSolvers)
    • The "SPICE" of the ElectroMagnetic world.
    • E.M. Workbench, FasterCap, FastCap2, FastHenry2, FastModel

Verification

  • Netgen
    • A circuit netlist comparison (LVS) and netlist conversion tool.
  • SymbiYosys (Clifford Wolf)
    • Front-end for Yosys-based formal verification flows.

Layout

  • Magic
    • A VLSI layout editor, extraction, and DRC tool.
  • KLayout
    • A high performance layout viewer and editor.
  • OpenMPL
    • An open source layout decomposition tool.

PDK and IP

  • FreePDK (NC State)
    • An open-source, Open-Access-based PDK for the 45nm technology node and the Predictive Technology Model.
  • POSH OpenFPGA (UofU)
    • A FPGA IP generator using XML-based architecture description including three parts: FPGA-Verilog, FPGA-SPICE, FPGA-Bitstream.
  • OpenRAM (UCSC)
    • An open-source memory compiler for VLSI circuits.
  • LibreCores
    • A digital hardware design community for creating and distributing IP cores in the open source spirit.
  • OpenCores
    • The reference community for Free and Open Source gateware IP cores.

Parsers

  • HDL (Verilog, VHDL, etc.)
    • Icarus Verilog, a Verilog simulation and synthesis tool compiling source code written in Verilog (IEEE-1364) into some target format
    • verilog-parser, a parser for the IEEE 1364-2001 verilog standard
    • pyverilog, a hardware design processing toolkit for Verilog HDL including verilog parser, dataflow analyzer, control-flow analyzer and code generator
    • hdlparse, a simple package implementing a rudimentary parser for VHDL and Verilog
  • LEF/DEF
  • Liberty
  • SDC

Open Access Tools (binary only)

ASIC Flow

FPGA Flow

High-level Synthesis

  • FuseSoC
    • A package manager and a set of build tools for HDL code.

Placement

  • ePlace (UCSD)
    • An electrostatics based placer using Nesterov's method.
  • NTUplace (NTU)
    • A ratio partitioning based placer for large-scale mixed-size designs.
  • FastPlace (Iowa State)
    • An Analytical Placer for Large-scale VLSI Circuits.
  • mPL6 (UCLA)
    • Constrained placement by multilevel optimization.
  • Dragon (UCLA)
    • A fast, effective standard-cell placement tool for both variable-die and fixed-die ASIC design.
  • Capo (UMich)
    • A fast and high-quality routability-driven placer for standard-cell ASICs.

Parsers

  • Liberty