Pinned Repositories
avmm_sha3
avst_adder
Example setup for UVM driven Icarus Verilog Simulation
avst_adder_vl
Reference eUVM testbench for verilator
avst_keccak
UVM Testbench for Keccak sha3 core downloaded from Opencores https://opencores.org/projects/sha3
euvm
Vlang port of UVM (Universal Verification Methodology)
goossens-book-ip-projects
this repository contains all the ip projects presented in the HLS/RISC-V/Computer Architecture book written by Goossens and published by Springer
meta-de10-nano
RISC-V-Assembly-Language-Programming
Source Code
sv-snippets
Snippets for Emacs and Vim
verlang
puneet's Repositories
puneet/euvm
Vlang port of UVM (Universal Verification Methodology)
puneet/goossens-book-ip-projects
this repository contains all the ip projects presented in the HLS/RISC-V/Computer Architecture book written by Goossens and published by Springer
puneet/RISC-V-Assembly-Language-Programming
Source Code
puneet/avst_adder
Example setup for UVM driven Icarus Verilog Simulation
puneet/axi4reg
AXI4 VIP for Reg Verifiation
puneet/bare-metal
bare-metal example code for arm,riscv
puneet/boolector
A Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions.
puneet/cmsgen
CMSGen, a fast uniform-like sample generator
puneet/crave
Constrained RAndom Verification Enviroment (CRAVE)
puneet/cryptominisat
An advanced SAT solver
puneet/ctags
A maintained ctags implementation
puneet/D-YAML
YAML parser and emitter for the D programming language
puneet/dma_ip_drivers
Xilinx QDMA IP Drivers
puneet/dmd
dmd D Programming Language compiler
puneet/druntime
Low level runtime library for the D programming language
puneet/dstep
A tool for converting C and Objective-C headers to D modules
puneet/ELFIO
ELFIO - ELF (Executable and Linkable Format) reader and producer implemented as a header only C++ library
puneet/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
puneet/kode-mono
The Kode Mono Typeface @ Google Fonts
puneet/PeakRDL-euvm
Euvm plugin for SystemRDL's PeakRDL tool.
puneet/PeakRDL-uvm
Generate UVM register model from compiled SystemRDL input
puneet/phobos
The standard library of the D programming language
puneet/riscv-bare-metal
RISC-V bare metal on QEMU
puneet/riscv-dv
Random instruction generator for RISC-V processor verification
puneet/riscv-hello-uart
Minimal bare-metal RISC-V assembly code with UART output for execution in QEMU
puneet/riscv-isa-sim
Spike, a RISC-V ISA Simulator
puneet/riscv-opcodes
RISC-V Opcodes
puneet/riscv32-bare-metal-qemu
Bare minimum setup required to run bare metal riscv32 with qemu
puneet/serpentos.com
Primary website, statically generated using D
puneet/verilator
Verilator open-source SystemVerilog simulator and lint system