Pinned Repositories
crazy-verilog
openwifi
open-source IEEE802.11/Wi-Fi baseband chip/FPGA design
openwifi-hw
FPGA/hardware design of openwifi
rex1168.github.io
riffa
The RIFFA development repository
SpinalHDL_Chinese_Doc
Translated SpinalHDL-Doc(v1.7.2) into Chinese
verilog-axi
Verilog AXI components for FPGA implementation
verilog-dsp
Verilog digital signal processing components
qiyefusheng's Repositories
qiyefusheng/crazy-verilog
qiyefusheng/rex1168.github.io
qiyefusheng/SpinalHDL_Chinese_Doc
Translated SpinalHDL-Doc(v1.7.2) into Chinese
qiyefusheng/verilog-axi
Verilog AXI components for FPGA implementation
qiyefusheng/verilog-dsp
Verilog digital signal processing components
qiyefusheng/openwifi
open-source IEEE802.11/Wi-Fi baseband chip/FPGA design
qiyefusheng/openwifi-hw
FPGA/hardware design of openwifi
qiyefusheng/riffa
The RIFFA development repository