This repository contains FPGA prototype of fully functional RISC-V Linux server with networking, online Linux package repository and daily package updates. It includes scripts and sources to generate RISC-V SoC HDL, Xilinx Vivado project, FPGA bitstream, and bootable SD card. The SD card contains Berkeley Boot Loader (aka RISC-V Proxy Kernel), U-Boot, Linux kernel and Debian root FS. Linux package repositories and regular updates are provided by Debian. Over 90% of packages of the whole Debian collection are available for download.
Also can be used to run bare-metal or RTOS software.
The project is used as a reference design to validate RISC-V support in Eclipse TCF.
Xilinx VC707 or Digilent Nexys Video board.
VC707 allows to prototype more powerful system: 2X cores (4 vs 2), 2X memory (1GB vs 512MB), 2X CPU clock frequency (100MHz vs 50MHz).
Nexys Video is several times less expensive, academic discount is avaialble.
Ubuntu 18 LTS machine is recommended. sudo access required.
Vivado 2019.2 or Vitis 2019.2 or Vitis 2020.1.
Nexys Video is supported by free version of Vivado. VC707 requires Vivado license.
If using Nexys Video, install Vivado Board Files for Digilent FPGA Boards.
sudo apt install git make
git clone https://github.com/eugene-tarassov/vivado-risc-v.git
cd vivado-risc-v
make apt-install
make update-submodules
source /opt/Xilinx/Vivado/2020.1/settings64.sh
make CONFIG=rocket64b2 BOARD=nexys-video bitstream
For VC707, use BOARD=vc707
Use USB SD card reader to connect SD card to the workstation, and run:
./mk-sd-card
The script looks for USB memory device and asks confirmation before using it. Make sure to confirm right SD card device - all old data will be erased.
- Open Vivado
source /opt/Xilinx/Vivado/2020.1/settings64.sh
make CONFIG=rocket64b2 BOARD=nexys-video vivado-gui
- Open the hardware manager and open the target board
- Select Tools - Add Configuration Memory Device
- Select the following device:
- Nexys Video: Spansion s25fl256xxxxxx0
- VC707: Micron mt28gu01gaaxle
- Add configuration file:
- Nexys Video: workspace/rocket64b2/nexys-video-riscv.mcs
- VC707: workspace/rocket64b2/vc707-riscv.mcs
- Press Ok. Flashing will take a couple of minutes.
- Right click on the FPGA device - Boot from Configuration Memory Device (or press the program button on the board)
See the board and Vivado docs for more details.
Host name: debian
User login and password: debian debian
Root login and password: root root
You can login over UART console:
sudo miniterm /dev/ttyUSB0 115200
or, after Linux boot, over SSH:
ssh debian@debian
Open Vivado:
source /opt/Xilinx/Vivado/2020.1/settings64.sh
make CONFIG=rocket64b2 BOARD=nexys-video vivado-gui
The IO block in the design is the best place to add device controllers, like GPIO. See AXI Uartlite as an example, connect your IP to AXI interconnect and interrupts. Validate and synthesize the design, but don't build bitstream yet - device tree and RISC-V HDL need to be updated first.
Close Vivado.
For example, for Xilinx GPIO, the config should contain line:
CONFIG_GPIO_XILINX=y
If necessary, change config, then rebuild Linux kernel and bootloader:
make linux bbl
./mk-sd-image -r debian-riscv64-boot
Copy debian-riscv64-boot/extlinux directory to the SD card.
Note: don't change files in the project submodules: linux-stable, u-boot, riscv-pk or rocket-chip. Such changes are lost when the project is rebuilt.
For details on Xilinx drivers, see Linux Drivers.
Add device description in the "soc {...}" section. For example, GPIO description can look like this:
gpio: gpio@60030000 {
#gpio-cells = <2>;
compatible = "xlnx,xps-gpio-1.00.a";
gpio-controller ;
interrupt-parent = <&L2>;
interrupts = <4>;
reg = < 0x60030000 0x10000 >;
xlnx,all-inputs = <0x0>;
xlnx,dout-default = <0x0>;
xlnx,gpio-width = <0x8>;
xlnx,interrupt-present = <0x1>;
xlnx,is-dual = <0>;
xlnx,tri-default = <0xffffffff>;
};
Make sure the description matches your design. In particular, check addresses and interrupt numbers.
make CONFIG=rocket64b2 BOARD=nexys-video bitstream
Program the FPGA or the board flash memory.
Prebuilt FPGA bitstream and SD card image are available in the releases area.
Rocket Chip is used as RISC-V implementation: UC Berkeley Architecture Research - Rocket Chip Generator. Rocket Chip is configured to include virtual memory, instruction and data caches, coherent interconnect, floating point, and all the relevant infrastructure. See rocket.scala for Rocket Chip configuration classes.
RISC-V SoC in this repo contains bootrom, which differ from original Rocket Chip bootrom. The modified bootrom contains SD card boot loader and extended device tree.
RISC-V SoC in this repo contains DDR, UART, SD and Ethernet controllers. DDR and UART are provided by Vivado, SD and Ethernet are open source Verilog.
SD controller implements SD HS (High Speed) specs, 25MB/s read/write speed.
Ethernet controller is based on Verilog Ethernet Components project, which is a collection of Ethernet-related components for gigabit, 10G, and 25G packet processing.
Linux kernel and U-Boot use device tree, which is stored in RISC-V bootrom in FPGA. So, same SD card should boot OK on any board or RISC-V configuration.
Nexys Video board can be configured to load FPGA bitstream from SD card.
The device tree contains Ethernet MAC address, which is not unique. It might be necessary to rebuild bitstream with different MAC, see Makefile for details.
If not using provided SD card image: the bootrom loads and executes boot.elf file from SD card DOS partition. boot.elf is regular executable ELF, it can contain any software suitable for RISC-V RV64 M mode. In case of Linux boot, boot.elf contains Berkeley Boot Loader and U-Boot.
The Makefile creates Vivado project directory, e.g. workspace/rocket64b2/vivado-nexys-video-riscv. You can open the project in Vivado GUI to see RISC-V SoC structure, make changes, add peripherals, rebuild the bitstream. The SoC occupies about 60% of FPGA, leaving plenty of space for experiments and developing additional hardware.
RISC-V SoC in this repo uses BSCAN block to support both RISC-V debugging and FPGA access over same JTAG cable.