Pinned Repositories
yosys-f4pga-plugins
Plugins for Yosys developed as part of the F4PGA project.
ql_designs
Opensource designs for testing
quicklogic-fpga-toolchain
Open Source FPGA toolchain and documentation for QuickLogic devices and eFPGA IP
s3-gateware
Gateware (HDL IPs) for EOS S3 MCU+eFPGA SoC
yosys-f4pga-plugins
Plugins for Yosys developed as part of the F4PGA project.
serv
SERV - The SErial RISC-V CPU
verilog-divider
a super-simple pipelined verilog divider. flexible to define stages
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
yosys-symbiflow-plugins
Plugins for Yosys developed as part of the SymbiFlow project.
rakeshm75's Repositories
rakeshm75/serv
SERV - The SErial RISC-V CPU
rakeshm75/verilog-divider
a super-simple pipelined verilog divider. flexible to define stages
rakeshm75/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
rakeshm75/yosys-symbiflow-plugins
Plugins for Yosys developed as part of the SymbiFlow project.