/MIPS-Microprocessor

16-bit MIPS Pipelined Processor in Verilog on Xilinx. Can perform 28 different operations. Tested by dumping on an FPGA.

Primary LanguageVerilogMIT LicenseMIT

MIPS-Microprocessor

Successfully integrated 16-bit MIPS Pipelined Processor in Verilog on Xilinx . The processor can perform 28 different operations identified by unique opcodes. The operations were successfully executed using an FPGA.

Different modules implemented and then integrated into working MIPS microprocessor based on RISC Architecture. Each verilog file for a block is supported with a corresponding test banch file.

Implemented modules:

  1. ALU Block
  2. Data Memory Block
  3. Jump Control Block
  4. Program Memory Block
  5. Register Bank
  6. Stall Control Block
  7. Write Back Block