/ComputerArchitecture

Works of all the labs of Computer Architecture. Contains single-cycle, and pipelined ARM architecture verilog code.

Primary LanguageVerilog

ComputerArchitecture Labs

Works of all the labs of Computer Architecture while I went through the course at BITS Pilani K K Birla Goa Campus under Dr. Biju K Raveendran.

Here are the contents of each lab:

  1. Lab 1 : Register File
  2. Lab 2 : 8bit Shifter and basic ALU circuit
  3. Lab 3 : Single cycle Implementation
  4. Lab 4 : Pipelined Architecture implementation
  5. Lab 5 : Pipeline with Data Forwarding and Hazard detection.

All the codes are in the respective folders and they contain a readme of themselves. Moreover, I think if you're interested in any of the above codes, you should download and see corresponding lab's pdf which contains schematic diagram, notations of all the modules being used in the code, as well as a testbench and output screen.

Hope this helps.

Bugs

Though I don't think any, and the codes are well documented also, if you find something, fix it up and issue a PR or just let me know by opening an issue.

Improvements

I am not spending much time on Computer Architecture and have been more interested in AI lately, and hence I'm not making any additions to these codes now. However, they're here so you can. Fork and make them better!

Author

Bhavul Gauri